Real-time test controller

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C714S718000

Reexamination Certificate

active

06338148

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to systems and methods for diagnostic testing performed during a manufacturing process. More particularly, the present invention relates to methods and apparatus for controlling diagnostic testing processes.
2. Description of the Prior Art and Related Information
Practically all manufactured goods undergo some testing to ensure that manufacturing defects are not present. Also, testing may be necessary to ensure that the goods perform up to a certain level, such as minimum design specifications, military/government contract specifications, etc. In the case of complex manufactured goods, certain flaws or failure to meet design specifications may only be detectable after final assembly, through one of a series of diagnostic tests.
For example, this is particularly true in the manufacture of computers, and computer related products, which often include numerous parts manufactured by independent suppliers. A manufacturer of computer products using parts supplied by third parties generally individually tests such parts as a routine matter. However, flaws in such parts may only be detectable when functioning together with the overall computer system. Further, a circuit board for a computer can require hundreds, and possibly thousands, of electrical connections to be made. It is often necessary for each connection to be tested, followed by testing of the overall board.
Normally, there are numerous levels of diagnostic tests run during a testing process, whether at a final stage of assembly or an intermediate stage, each test seeking to detect a particular fault or faults. Diagnostic test sequences are typically determined by a diagnostic engineer prior to manufacturing, with the same test sequences being run for the entire life-cycle of the product.
In the manufacturing process, time can often directly translate into money. This is a significant concern to most, if not all, manufacturers. In many cases, an hour or more of non-production test time can be wasted if a diagnostic test which appears late in the testing process fails.
For example, in the manufacturing of a typical circuit board (or Printed Wire Assembly-PWA), testing costs can run from $80-$100 per hour, or more, for each PWA. Wasted testing time can thus be responsible for a significant amount of unnecessary costs being added to each device under test. Any reduction in testing time can result in significant cost savings for the finished product and result in considerable cost savings to the manufacturer. Unfortunately, prior art testing procedures do not adequately address the problems of wasted testing time and thus result in considerable time and money being wasted due to an inefficient, rigid testing process.
Accordingly, a need presently exists for an improved diagnostic testing routine which is efficient, flexible, adaptive, and which addresses the above-noted problems with typical diagnostic testing procedures.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for controlling, in real-time, the diagnostic testing of a manufactured product, resulting in optimization of the diagnostic test sequence by optimizing the order in which the diagnostic tests are run.
During manufacturing, several diagnostics are often run against a product, with each diagnostic being designed to identify a specific fault. In an ideal manufacturing process, faults occur in a random fashion. In such a case, the sequence in which diagnostic tests are run makes no difference since it is not possible to predict which fault will occur next. In reality, however, faults often occur in “clumps” which may be defined as “non-random fault clusters” or “NRFCs.” If the diagnostic test which detects a fault which is part of a NRFC is run late in the testing process, a significant amount of testing will be wasted due to the high likelihood of failure of the test associated with the NRFC.
When a NRFC occurs in the testing process as discussed above, there is suddenly a single diagnostic test which fails repeatedly. With the typical diagnostic test system, there is no way to control in real-time when the diagnostic which would detect the NRFC fault is run in the test sequence since the sequence is preset by the diagnostic engineer during the design phase of the product.
The present invention provides a controller for controlling testing procedures in a manufacturing or test facility. The controller includes a real-time diagnostic optimizer which detects non-random fault clusters, or NRFCS, determines which diagnostics detect the NRFC faults, produces an optimized sequence of diagnostics which reflect the detected NRFCs, and transfers the optimized sequence of tests to the device which is being tested.
In this fashion, when an NRFC exists, it is tested for first. In most cases, the dominant fault is detected by the first few diagnostics, and the test process terminates, allowing technicians to quickly address the detected fault. This system significantly reduces test time and results in significant time/cost savings.
In a preferred embodiment, the test controller of the present invention incorporates five distinct components, all of which operate under a common hardware configuration. These components include: a command line interface with the component under test; diagnostics which may or may not reside in the component under test; a test failure database; a command module (CM); and a diagnostic optimizer.
In general, when a board fails a test, data relating to the failure type, the failing diagnostic, date and time, and any other desired data, are logged into the failure database. This can be done either automatically by the controller or manually by a test technician. The failure database acts as a repository for the failure data, and later for the repair data required to correct the failure. The failure database collects this data sequentially, according to entry date.
As each new test is performed, the CM in the controller contacts the diagnostic optimizer which is responsible for querying the failure database. The diagnostic optimizer determines a fault spectrum of the most recent failures. The fault spectrum enables the diagnostic optimizer to detect non-random fault clusters which occurred during previous testing routines.
The system components of the controller work in a repeating real-time cycle with the failure database continuously logging failures, the diagnostic optimizer searching the failure database to generate an optimized sequence of diagnostics, the command module requesting this data from the diagnostic optimizer and delivering it to the command line interface, and finally, the command line interface using the optimized data to re-sequence the diagnostics to match the optimized testing routine which is built around detected non-random fault clusters.
The present invention thus provides a test controller for providing an optimized testing sequence which will detect, in a more efficient and cost-effective manner, failures occurring in products under test. This allows the present invention to eliminate wasted time in the testing process and to concentrate on known testing difficulties, thereby providing the manufacturer, and ultimately the consumer, with a substantial savings.
Additional features and advantages of the present invention will be appreciated by a review of the following detailed description of the present invention when considered in light of the drawings.


REFERENCES:
patent: 4285059 (1981-08-01), Burlage et al.
patent: 4453248 (1984-06-01), Ryan
patent: 4642782 (1987-02-01), Kemper et al.
patent: 4654852 (1987-03-01), Bentley et al.
patent: 4727549 (1988-02-01), Tulpule et al.
patent: 4841456 (1989-06-01), Hogan, Jr. et al.
patent: 5031177 (1991-07-01), Jurgen
patent: 5036479 (1991-07-01), Prednis et al.
patent: 5090014 (1992-02-01), Polich et al.
patent: 5107499 (1992-04-01), Lirov et al.
patent: 5107500 (1992-04-01), Wakamoto et al.
patent: 5233610 (1993-08-01), Nakayama et al.
patent: 5381417 (1995-01-

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Real-time test controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Real-time test controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Real-time test controller will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2818307

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.