Method for forming gate electrodes of semiconductor device...

Details Method for forming gate electrodes of semiconductor device... Method for forming gate electrodes of semiconductor device...

1999-12-17

2002-01-22

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S652000, C438S653000, C438S654000, C438S655000, C438S657000

Reexamination Certificate

active

06340629

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for forming gate electrodes of semiconductor device, especially for gate electrodes of a semiconductor device, such as over 1 Gb DRAM(dynamic random access memory) that requires high integrity and high operation speed.
2. Description of the Related Art
The semiconductor memory device is generally divided into a read/write memory and a read-only-memory(ROM). The read/write memory is also divided into a DRAM and an SRAM(static random access memory). The DRAM is the most advanced device in point of integrity since one unit cell comprises one transistor and one capacitor.
In the meantime, 256 Mb DRAM has been developed since memory capacity was raised by four times in every three years due to fast development in the integrity, and also various studies on 1 Gb DRAM are in progress. As the DRAM is highly integrated, size of a cell reading electrical signals and writing is also reduced in proportion to the reduction in size. For example, the size of 1 Gb DRAM cell is approximately 0.8 &mgr;m
2
. Accordingly, a required line width of a gate electrode corresponding to said size is reduced very much. As a result, a material for gate electrode such as a conventional polysilicon or a tungsten silicide WSix can not realize low resistance by means of fine line width which is required by the over 1 Gb DRAM.
Namely, up to now, a doped polysilicon has been used for the gate electrode of a semiconductor device, and a tungsten silicide is deposited on the polysilicon in order to lower the resistivity of the electrode. However, the resistivity of tho tungsten silicide thin film is approximately 100 &mgr;&OHgr;·cm which is still high, and further reduction in the resistivity of the gate electrode is required so as to obtain a device capable of driving in over 1 Gb DRAM with fine line width. Accordingly, there have been a number of studies on forming a word line by means of the tungsten whose resistivity is approximately 10 &mgr;&OHgr;·cm.
Meanwhile, in order to form the tungsten on a lower polysilicon, there should be formed a tungsten nitride(WN) layer as a diffusion barrier layer so that a reaction between tungsten and polysilicon may be prevented. Now, tungsten can not be deposited on the tungsten nitride(WN) layer by the chemical vapor deposition(CVD) process, therefore the physical vapor deposition(PVD) process is used. According to the PVD process, however a thin film is deposited not only on the wafer but on other portions of a chamber. As thickness of the deposited thin film within the chamber is increased, they function as particle source. To remove the particle source, an equipment for the PVD process is disjointed into pieces, and then washed. However, this process increases downtime of equipment thereby lowering productivity and the yield is also lowered.
SUMMARY OF THE INVENTION
Accordingly, this invention is provided to solve foregoing problems. It is the object of the present invention to provide a method for forming gate electrodes of a high integration memory device that uses especially tungsten gate electrode formed on the tungsten nitride(WN) layer, not by the PVD process but by the CVD process.
The method for forming gate electrodes of a semiconductor device as provided above to accomplish the foregoing object, comprises the steps of: forming a gate insulating layer on a semiconductor substrate, a silicon layer on the gate insulating layer; forming a tungsten nitride(WN) layer on the silicon layer; forming a first tungsten layer at an upper portion of the tungsten nitride layer and a silicon tungsten nitride layer at a lower portion contacted with the silicon layer by thermally treating the tungsten nitride(WN) layer; and forming a second tungsten layer on the first tungsten layer by using the first tungsten layer as a nucleation layer according to a chemical vapor deposition process.


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