Driving circuit of nonvolatile ferroelectric memory device...

Details Driving circuit of nonvolatile ferroelectric memory device... Driving circuit of nonvolatile ferroelectric memory device...

2000-11-28

2002-01-01

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S233100, C365S226000

Reexamination Certificate

active

06335877

ABSTRACT:

BACKGROUND OF THE INVENTION
This application claims the benefit of Application No. P
2000-7354
, filed in Korea on Feb. 16, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a nonvolatile ferroelectric memory device, and more particularly, to a driving circuit of a nonvolatile ferroelectric memory device and a method for driving the same.
2. Background of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM) has a data processing speed equal to a dynamic random access memory (DRAM) and retains data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices with similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1
shows a hysteresis loop of a general ferroelectric. As shown in
FIG. 1
, even if polarization induced by the electric field has the electric field removed, data is maintained at a certain amount (i.e., d and a states) without being erased due to the presence of residual polarization (or spontaneous polarization). A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the d and a states to 1 and 0, respectively.
A related art nonvolatile ferroelectric memory device will now be described.
FIG. 2
shows a unit cell of a related art nonvolatile ferroelectric memory.
As shown in
FIG. 2
, the related art nonvolatile ferroelectric memory includes a bitline B/L formed in one direction, a wordline W/L formed to cross the bitline, a plate line P/L spaced apart from the wordline in the same direction as the wordline, a transistor T
1
with a gate connected with the wordline and a source connected with the bitline, and a ferroelectric capacitor FC
1
. A first terminal of the ferroelectric capacitor FC
1
is connected with a drain of the transistor T
1
and second terminal is connected with the plate line P/L.
The data input/output operation of the related art nonvolatile ferroelectric memory device will now be described.
FIG. 3
a
is a timing chart illustrating the operation of the write mode of the related art nonvolatile ferroelectric memory device, and
FIG. 3
b
is a timing chart illustrating the operation of read mode thereof.
During the write mode, an externally applied chip enable signal CSBpad is activated from high state to low state. At the same time, if a write enable signal WEBpad is applied from high state to low state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from low state to high state to select a cell.
A high signal in a certain period and a low signal in a certain period are sequentially applied to a corresponding plate line in a period where the wordline is maintained at high state. To write a logic value “1” or “0” in the selected cell, a high signal or low signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline.
In other words, a high signal is applied to the bitline, and if the low signal is applied to the plate line in a period where the signal applied to the wordline is high, a logic value “1” is written in the ferroelectric capacitor. A low signal is applied to the bitline, and if the signal applied to the plate line is high, a logic value “0” is written in the ferroelectric capacitor.
The reading operation of data stored in a cell by the above operation of the write mode will now be described. If an externally applied chip enable signal CSBpad is activated from high state to low state, all of bitlines become equipotential to low voltage by an equalizer signal EQ before a corresponding wordline is selected.
Then, the respective bitline becomes inactive and an address is decoded. The low signal is transited to the high signal in the corresponding wordline according to the decoded address so that a corresponding cell is selected.
The high signal is applied to the plate line of the selected cell to destroy data corresponding to the logic value “1” stored in the ferroelectric memory. If the logic value “0” is stored in the ferroelectric memory, the corresponding data is not destroyed.
The destroyed data and the data that is not destroyed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value “1” or “0”. In other words, if the data is destroyed, the “d” state is transited to an “f” state as shown in hysteresis loop of FIG.
1
. If the data is not destroyed, “a” state is transited to the “f” state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value “1” is output in case that the data is destroyed while the logic value “0” is output in case that the data is not destroyed.
As described above, after the sensing amplifier outputs data, to recover the data to the original data, the plate line becomes inactive from high state to low state at the state that the high signal is applied to the corresponding wordline.
In the aforementioned related art nonvolatile ferroelectric memory device, in case that the nonvolatile ferroelectric memory device is being used as a memory device in the system, the stable operation voltage area of the nonvolatile ferroelectric memory device and the operation voltage area of a system controller can be different.
That is, when the operation voltage area of the system controller is smaller than the operation voltage area of the nonvolatile ferroelectric memory device, the system controller generates a normal control signal at even state that the system power supply abnormally descends.
In even case that the voltage descends, the system controller is capable of operating normally, while the nonvolatile ferroelectric memory device is not capable of operating normally. Nevertheless, since the nonvolatile ferroelectric memory device reads data stored in the cell by destroying in read mode, a read cycle can be terminated before the destroyed data in the reading operation are restored at the state of abnormal descending of power supply voltage or low voltage.
Accordingly, a method for retaining data is specially required in the nonvolatile ferroelectric memory device even in reading.
For example, a method using a low voltage sensing circuit can be used as the method for retaining data.
FIG. 4
illustrates a schematic driving circuit of the related art nonvolatile ferroelectric memory device.
For reference,
FIG. 4
is a circuit diagram of a low voltage sensing circuit.
As shown in
FIG. 4
, the related art nonvolatile ferroelectric memory device includes first transistor and second transistor T
1
, T
2
serially connected between a power supply voltage terminal Vcc and a ground voltage terminal Vss, and the gates thereof connected with each other, a third transistor T
3
controlled by output voltage of the first transistor T
1
and a drain thereof connected with the ground voltage terminal Vss, a fourth transistor T
4
having a source connected with the power supply voltage terminal Vcc, a drain connected with a source of the third transistor T
3
, and a gate connected with the ground voltage terminal Vss, a first inverter INV
1
for inverting output voltage of the third transistor T
3
, a second inverter INV
2
serially connected with the first inverter INV
1
and inverting the output voltage of the third transistor T
3
, a third inverter INV
3
for inverting output of the second inverter INV
2
, a fourth inverter INV
4
for inverting output of the third inverter INV
3
and outputting as a first output signal OUT
1
, a fifth inverter INV
5
for inverting output signal of the first inverter INV
1
, a fifth transistor T
5
controlled by output signal of the fifth inverter INV
5
, a source thereof connected with the power supply voltage terminal Vcc, a drain thereof connect

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