Semiconductor memory device suitable for merging with logic

Details Semiconductor memory device suitable for merging with logic Semiconductor memory device suitable for merging with logic

2000-06-09

2002-07-09

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030

Reexamination Certificate

active

06418067

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and specifically to a semiconductor memory device suitable for merging with a logic such as a logic device or a microprocessor. More specifically, the present invention is related to an arrangement of a data write/read portion of a logic-merged DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
In recent years, a DRAM built-in system LSI (Large Scale Integration) having a DRAM and a logic device or a microprocessor integrated on the same semiconductor substrate has become widely adopted. The DRAM built-in system LSI has the following advantages over the conventional system having a discrete DRAM and a logic device soldered onto a printed-circuit board:
(1) There is no need to take into account the pin terminals of the discrete DRAM, so that wider space may be used for the data bus between a DRAM and a logic, and an improved data transfer rate is achieved, leading to an improved system performance;
(2) The data bus formed on a semiconductor substrate has a smaller parasitic capacitance than the wire on a printed-circuit board, so that the charge/discharge current of a signal line can be reduced, while the operating current consumed during data transfer can also be reduced; and
(3) The package can be unified, and the data bus wiring and the control signal wiring on the printed-circuit board can be reduced in number so that smaller area is occupied on the printed-circuit board.
FIG. 58
is a diagram representing an example of an arrangement of a conventional DRAM built-in system LSI. In
FIG. 58
, the DRAM built-in system LSI has a logic circuit LG and a DRAM macro integrated on the same semiconductor substrate chip CH.
The DRAM macro includes memory arrays MA
0
and MA
1
, each having a plurality of memory cells arranged in a matrix of rows and columns; row decoders XD
0
and XD
1
provided corresponding to memory arrays MA
0
and MA
1
for selecting addressed rows of the corresponding memory arrays MA
0
and MA
1
; column decoders YD
0
and YD
1
provided corresponding to memory arrays MA
0
and MA
1
for selecting addressed columns of memory arrays MA
0
and MA
1
; data paths DP
0
and DP
1
for communicating data with the memory cell columns selected by column decoders YD
0
and YD
1
; and a control circuit CG for controlling the data access operation to memory arrays MA
0
and MA
1
.
Data paths DP
0
and DP
1
are coupled to logic circuit LG via data buses DB
0
and DB
1
, and control circuit CG is coupled to logic circuit LG via a control bus CTB. In
FIG. 58
, each of data buses DB
0
and DB
1
separately communicates 128-bit write data (D) and 128-bit read data (Q).
In the DRAM built-in system LSI shown in
FIG. 58
, row decoders XD
0
and XD
1
are disposed orthogonal to column decoders YD
0
and YD
1
. Upon selecting the columns of memory arrays MA
0
and MA
1
with column decoders YD
0
and YD
1
, data paths DP
0
and DP
1
can be coupled to the selected columns of memory arrays MA
0
and MA
1
in the shortest distance. In addition, since the DRAM macro and logic circuit LG are integrated on the same semiconductor chip CH, data buses DB
0
and DB
1
are not in any way limited with respect to the pitch condition and number of pin terminals so that a wide bus can be implemented.
FIG. 59
is a schematic representation of an arrangement of memory arrays MA
0
and MA
1
shown in FIG.
58
. Since these memory arrays MA
0
and MA
1
have identical arrangement, they are generically shown as memory array MA in FIG.
59
. Memory array MA includes a plurality of memory cell blocks MCB arranged in a matrix of rows and columns. Though not specifically shown, memory cells are arranged in a matrix of rows and columns within these memory cell blocks MCB.
Local IO line pair groups LIOs are provided corresponding to each of memory cell blocks MCB for communicating data with the corresponding memory cell blocks. A local IO line pair LIO communicates signals complementary one another. Moreover, a sense amplifier group SAs is arranged corresponding to each of memory cell blocks MCB. Sense amplifier group SAs has a shared sense amplifier arrangement and is shared by the memory cell blocks adjacent to one another in the column direction. These sense amplifier groups SAs includes sense amplifier circuits SA provided corresponding to the respective columns of the corresponding memory cell blocks, and perform sense, amplification, and latching of data of the columns of the corresponding memory cell blocks during activation. Sense amplifier group SAs is selectively coupled to the corresponding local IO line pair group LIOs.
Word line group WLs is disposed in common to memory cell blocks MCB arranged in alignment in the row direction. In operation, one word line WL of word line group WLs contained in one row block (or the block consisting of the memory cell blocks arranged in alignment in the row direction) is driven to the selected state.
Global IO line pairs GIO
0
to GIO
127
that extend in the column direction are disposed in regions between the memory cell blocks adjacent to one another in the row direction and a region outside of the memory cell blocks (these regions hereinafter referred to as inter-block regions). Four global IO line pairs are arranged in common to the memory cell blocks aligned in the column direction. Four local IO line pairs LIO are provided to each memory cell block, and a group of the four local IO line pairs LIOs correspondingly provided to each memory cell block MCB in one row block are coupled to the corresponding global IO line pairs via IO switches IOSW, respectively.
Each of global IO line pairs GIO
0
to GIO
127
transmits complementary signals, is coupled to a data path shown in
FIG. 58
, and is coupled to logic circuit LG via a write/read circuit within the data path.
Column select lines CSL are arranged extending in the column direction over memory cell array MA in the same interconnection layer as global IO line pairs GIO
0
to GIO
127
. Column select line group CSLs are shared by memory cell blocks MCB disposed in alignment in the column direction. By IO switches IOSW, local IO line pair groups LIOs of a selected row block are coupled to global IO line pairs GIO
0
to GIO
127
, while local IO line pair groups LIOs of non-selected row blocks are disconnected from global IO line pairs GIO
0
to GIO
127
. Thus, four columns are simultaneously selected in each column block (or the block consisting of the memory cell blocks arranged in alignment in the column direction), and four local IO line pairs LIO are respectively coupled to the corresponding global IO line pairs.
In the array arrangement shown in
FIG. 59
, global IO line pairs GIO
0
to GIO
127
are coupled to logic circuit LG via the data paths. Therefore, increasing the bus width of data buses DB
0
and DB
1
between the DRAM macro and the logic circuit means increasing the number of global IO line pairs. In order to increase the number of global IO line pairs, the number of inter-block regions needs to be increased. A global IO line pair is a complementary signal line pair, and the increase in number of inter-block regions results in the increase in the area occupied by the global IO line pairs in a memory cell array and in the increase in the area of the region occupied by transfer gates connecting global IO line pairs GIO and local IO line pair LIO, which leads to a greater chip area.
FIG. 60
is a schematic representation of another conventional DRAM built-in system LSI. The arrangement shown in
FIG. 60
is presented, for instance, by Yabe et al. in Digest of Technical Papers, 1999 IEEE ISSCC, on pp. 72 to 73 and p. 415.
In the DRAM built-in system LSI shown in
FIG. 60
, row decoders XD
0
and XD
1
as well as column decoders YX
0
and YX
1
are disposed in the region between memory arrays MA
0
and MA
1
. Thus, row decoders and column decoders are provided within the same region.
The column decoders are not disposed between memory arrays MA
0
and MA
1

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