Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-04-23
2002-09-24
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S096000, C327S212000
Reexamination Certificate
active
06456113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a scan flip-flop circuit for use in a scan test for detecting a fault in a semiconductor integrated circuit.
2. Description of the Related Art
Heretofore, scan tests for detecting faults in semiconductor integrated circuits such as LSI circuits or the like employ a scan flip-flop circuit as shown in
FIG. 1
of the accompanying drawings, for example.
As shown in
FIG. 1
, the conventional scan flip-flop circuit comprises selector circuit
1
having a normal logic input terminal and a scan logic input terminal, master latch circuit
2
, slave latch circuit
9
having a logic output terminal and a scan logic output terminal, and clock circuit
4
.
The scan logic output terminal is an output terminal dedicated to scan tests, and does not operate in a normal mode of operation, but operates only in a scan test.
Selector circuit
1
comprises transfer gates
11
,
12
.
Transfer gate
11
selectively passes and blocks normal logic input signal D inputted from the normal logic input terminal.
Transfer gate
12
selectively passes and blocks scan logic input signal SIN inputted from the scan logic input terminal.
Master latch circuit
2
comprises transfer gates
21
,
24
,
25
and inverters
22
,
23
.
Transfer gate
21
selectively passes and blocks a signal outputted from selector circuit
1
.
Inverter
22
inverts a signal that has passed through transfer gate
21
, and outputs the inverted signal.
Transfer gate
25
selectively passes and blocks a signal outputted from inverter
22
, and outputs the passed signal to slave latch circuit
9
in a subsequent stage.
Inverter
23
inverts a signal outputted from inverter
22
, and outputs the inverted signal.
Transfer gate
24
selectively passes and blocks a signal inputted from inverter
23
to inverter
22
.
Slave latch circuit
9
comprises inverters
91
,
92
,
95
and transfer gates
93
,
94
.
Inverter
91
inverts a signal outputted from master latch circuit
2
, and outputs the inverted signal as logic output signal Q from the logic output terminal.
Inverter
92
inverts a signal outputted from inverter
91
, and outputs the inverted signal.
Transfer gate
93
selectively passes and blocks a signal inputted from inverter
92
to inverter
91
.
Transfer gate
94
selectively passes and blocks a signal outputted from inverter
92
.
Inverter
95
inverts a signal that has passed through transfer gate
94
, and outputs the inverted signal as scan logic output signal SOUT from the scan logic output terminal.
Clock circuit
4
comprises inverters
41
,
42
,
43
,
44
.
Inverter
41
inverts clock signal CLK and outputs the inverted clock signal as clock signal AB.
Inverter
42
inverts a signal outputted from inverter
41
and outputs the inverted signal as clock signal A.
Inverter
43
inverts control signal SEL and outputs the inverted clock signal As control signal BB.
Inverter
44
inverts a signal outputted from inverter
43
and outputs the inverted signal as control signal B.
Clock signals AB, A and control signals BB, B thus generated control the transfer gates in selector circuit
1
, master latch circuit
2
, and slave latch circuit
9
.
Operation of the scan flip-flop circuit constructed as described above will be described below with reference to
FIG. 2
of the accompanying drawings.
First, a normal mode of operation of the scan flip-flop circuit will be described below.
When control signal SEL applied to clock circuit
4
goes low at time t=t
3
, control signal BB goes high and control signal B goes low. Therefore, in selector circuit
1
, transfer gate
11
is rendered conductive, outputting normal logic input signal D.
As clock signal CLK applied to clock circuit
4
is “Low”, clock signal AB is “High” and clock signal A is “Low”. Therefore, transfer gate
21
in master latch circuit
2
is rendered conductive. Consequently, normal logic input signal D outputted from selector circuit
1
is supplied to master latch circuit
2
and inverted and outputted by inverter
22
.
When clock signal CLK goes high at time t=t
4
, clock signal AB goes low and clock signal A goes high. Therefore, transfer gate
21
is rendered nonconductive, and transfer gates
24
,
25
are rendered conductive. The signal outputted from inverter
22
is latched and outputted to slave latch circuit
9
.
In slave latch circuit
9
, the signal supplied from master latch circuit
2
is inverted by inverter
91
, and the inverted signal is outputted as logic output signal Q from the logic output terminal.
When clock signal CLK goes low again at time t=t
5
, clock signal AB goes high and-clock signal A goes low. Consequently, transfer gate
93
is rendered conductive. Thus, logic output signal Q is latched and outputted.
In the normal mode of operation (when control signal SEL is “Low”), since control signal BB is “High” and control signal B is “Low”, transfer gate
94
is nonconductive. Therefore, the scan logic output terminal does not operate.
A scan test mode of operation of the scan flip-flop circuit will be described below.
In a scan test, when control signal SEL applied to clock circuit
4
goes high at time t=t
0
, control signal BB goes low and control signal B goes high. In selector circuit
1
, transfer gate
12
is rendered conductive, outputting scan logic input signal SIN.
As clock signal CLK applied to clock circuit
4
is “Low”, clock signal AB is “High” and clock signal A is “Low”. Therefore, transfer gate
21
in master latch circuit
2
is rendered conductive. Consequently, scan logic input signal SIN outputted from selector circuit
1
is supplied to master latch circuit
2
and inverted and outputted by inverter
22
.
When clock signal CLK goes high at time t=t
1
, clock signal AB goes low and clock signal A goes high. Therefore, transfer gate
21
is rendered nonconductive, and transfer gates
24
,
25
are rendered conductive. The signal outputted from inverter
22
is latched and outputted to slave latch circuit
9
.
In slave latch circuit
9
, the signal supplied from master latch circuit
2
is inverted by inverter
91
, and the inverted signal is outputted as logic output signal Q from the logic output terminal.
When clock signal CLK goes low again at time t=t
2
, clock signal AB goes high and clock signal A goes low. Consequently, transfer gate
93
is rendered conductive. Thus, logic output signal Q is latched and outputted.
In the scan test (when control signal SEL is “High”), since control signal BB is “Low” and control signal B is “High”, transfer gate
94
is rendered conductive. Therefore, the signal outputted from inverter
92
is inverted by inverter
95
, and the inverted signal is outputted as scan logic output signal SOUT from the scan logic output terminal.
The scan flip-flop circuit shown in
FIG. 1
has its scan logic output terminal connected to the scan logic input terminal of a next scan flip-flop circuit. All the scan flip-flop circuits are connected in series by their scan logic output terminals and scan logic input terminals. In a scan test, all the scan flip-flop circuits shift signals through their scan logic output terminals and scan logic input terminals.
In general scan flip-flop circuits, the scan logic output terminal operates in synchronism with the logic output terminal though the scan logic output terminal is not used in the normal mode of operation. Accordingly, the scan logic output terminal consumes electric power in the normal mode of operation.
In the scan flip-flop circuit shown in
FIG. 1
, however, transfer gate
94
is controlled by control signal SEL to stop operation of the scan logic output terminal in the normal mode of operation. As a result, the power consumption by the scan logic output terminal is relatively low.
Actually, however, when transfer gate
94
connected to the scan logic output terminal is rendered nonconductive, it outputs an intermediate potential that is applied to inverter
95
. As shown in
FIG. 2
, the intermediate potential is ou
Le Don Phu
NEC Corporation
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