Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-04-14
2002-07-02
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06415419
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a circuit designing method therefor, and more specifically to a semiconductor integrated circuit device such as an application specific integrated circuit (ASIC) internally including a circuit used at a testing time, and a circuit designing method therefor.
2. Description of Related Art
Recently, increase of the scale of the LSI (large scale integrated circuit) and complication of the internal functions are very remarkable. In addition, the speed-up of the processing and the increase in width of a data bus also become remarkable. Therefore, a test of an operation of the LSI has increased in importance. The increase of the functions incorporated in the LSI results in the increase of logic circuits incorporated in the LSI, and therefore, the circuits for testing these functions have inevitably increased. In general, the larger the circuit scale is, the required test time exponentially increases, and on the other hand, the precision of the test exponentially decreases.
Referring to
FIG. 1
, there is shown a layout diagram illustrating a first example of the prior art semiconductor integrated circuit device internally including the circuit used at the testing time. The prior art semiconductor integrated circuit device shown in
FIG. 1
includes a plurality of function blocks
11
formed on a semiconductor substrate (chip)
100
, and test dedicated input/output buses
13
also formed on the semiconductor substrate
100
, each of the input/output buses
13
supplying an input signal from an external test circuit to a corresponding function block and transferring an output signal from the corresponding function block to the external test circuit.
A method for testing this first prior art semiconductor integrated circuit device is that a predetermined test pattern is supplied from the external test circuit to a selected test dedicated input/output bus
13
so as to be given to the function block
11
to be put under test. An output signal generated in the function block
11
under test in response to the given test pattern is outputted through the test dedicated input/output bus
13
to the external test circuit. It is then determined whether or not the value of the output signal is equal to an expected value which was previously prepared. by means of a simulation at a designing stage for the same test pattern.
On the other hand, a logic circuit which is not connected to the test dedicated input/output buses
13
, is tested in such a manner that a predetermined test pattern is supplied to input terminals of the semiconductor integrated circuit device under test, and whether or not an expected value corresponding to the given test pattern appears on output terminals of the semiconductor integrated circuit device, is checked.
Now, a circuit designing method for the first prior art semiconductor integrated circuit device will be described with reference to
FIG. 2
which is a flow chart for illustrating the steps of the circuit designing method. First, after a chip specification is determined a circuit of a desired function block is designed (step P
1
). Then a circuit used for testing, the desired function block is designed (step P
4
). Thereafter a test pattern for the desired function block is prepared (step S
5
). In parallel, a “chip for test” is prepared on the basis of the result of the circuit design of the desired function block and the result of the circuit design of the circuit used for the testing (step S
6
). Finally, the “chip for test” is tested using, the test pattern prepared (step S
7
). If the result of the test is successful, the design is completed.
In this first prior art semiconductor integrated circuit device, since the test is executed for each one logic or function block, if the integration degree of the function block is elevated, namely, if the number of gates is increased, it becomes difficult to check all gates internally included in each function block by means of the test patterns given to each function block. Therefore, with an increased integration decree of each function block, the lowering of the failure detection percentage and the increase of the test time become remarkable. In addition, since one independent test dedicated input/output bus are formed for each function block. the number of required terminals and the occupied area inevitably increase.
In order to improve the above mentioned prior art semiconductor integrated circuit device, Japanese Patent Application Pre-examination Publication No. JP-A-06-109816 (an English abstract of which is available and the content of the English abstract is incorporated by reference in its entirety into this application) proposes a second prior art semiconductor integrated circuit device which is so configured to cause a plurality of function blocks to share one test dedicated input/output bus. In a logic LSI such as a gate array, according to JP-A-06-109816, the circuit is divided into a plurality of function blocks, and an output of each function block is provided with a buffer circuit having a data latch function and a scan path function allowing a received signal to pass without modification. The buffer circuit is controlled by a control signal so as to assume a selected one of the data latch function and the scan path function, and each buffer circuit is connected to a common test dedicated bus so that a test data can be directly supplied to or received from the buffer circuit.
However, even in this second prior art semiconductor integrated circuit device, similarly to the first prior art semiconductor integrated circuit device, if the integration degree of the function block is elevated. it becomes difficult to check all gates internally included in each function block by means of the test patterns given to each function block. In addition, the lowering of the failure detection percentage and the increase of the test the become remarkable. On the other hand. JP-A-06-109816 does not mention how the test dedicated bus is laid out. Therefore, although the number of required terminals can be surely reduced by JP-A-06-109816, the degree of increase in the area occupied by the test function including the buffer circuits and the test dedicated bus is unknown.
Furthermore, there is a third prior art semiconductor integrated circuit device intended to elevate the failure detection percentage. This third prior art semiconductor integrated circuit device uses a cross-check testing method which uses conventional test patterns and which checks an output voltage of all cell arrays in each test pattern. With this arrangement, not only output pins of the chip and the function blocks but also the inside of the circuit are observed in detail in order to elevate the failure detection percentage.
In this third prior art semiconductor integrated circuit device, however, a problem is encountered in that the number of test patterns required for the cross-check greatly increases. Therefore, the design time and the test time remarkably increase.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit device which has overcome the above mentioned problems of the prior art, and a circuit designing method therefor.
Another object of the present invention is to provide a semiconductor integrated circuit device capable of testing all functions and all circuit performance of all function blocks in the semiconductor integrated circuit device, without lowering the failure detection percentage and without increasing the test time, with a reduced number of input/output terminals and with a reduced area occupied for the test function, and a circuit designing, method therefor.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor integrated circuit device including a logic LSI formed on a semiconductor substrate and divided into a plurality of function blocks, each of w
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Corporation
Phan Trong
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