Method and apparatus for creating integrated circuit...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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Reexamination Certificate

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07386434

ABSTRACT:
An apparatus and method for generating test files for design verification of a simulated integrated circuit design such as a cache memory circuit, that involve steps of creating a series of functions, updating a data integrity buffer after each function is created, creating a series of integrity check functions from the data in the data integrity buffer, and writing the series of functions and the series of integrity check functions to a test file. This file can be compiled if necessary and executed by a software or hardware simulator.

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A. Chandra et al.; “AVPGEN—A Test Generator for Architecture Verification”, Jun. 1995, IEEE Transactions on Very Large Scale Integration Systems, vol. 3, No. 2, pp. 188-200.

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