Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2008-06-10
2008-06-10
Rodriguez, Paul L (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
Reexamination Certificate
active
07386434
ABSTRACT:
An apparatus and method for generating test files for design verification of a simulated integrated circuit design such as a cache memory circuit, that involve steps of creating a series of functions, updating a data integrity buffer after each function is created, creating a series of integrity check functions from the data in the data integrity buffer, and writing the series of functions and the series of integrity check functions to a test file. This file can be compiled if necessary and executed by a software or hardware simulator.
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Guill Russ
Johnson Charles A.
Marley Robert
Rodriguez Paul L
Shumaker & Sieffert PA
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