Semiconductor memory device with MOS transistors each having...

Details Semiconductor memory device with MOS transistors each having... Semiconductor memory device with MOS transistors each having...

2008-05-20

2008-05-20

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S189070

Reexamination Certificate

active

07376023

ABSTRACT:
A semiconductor memory device includes memory cells, a memory cell array, a first voltage generating circuit, a reference voltage generating circuit, and a first voltage control circuit. Each of the memory cells includes a first MOS transistor comprising a floating gate and a control gate formed on the floating gate. The memory cell array includes the memory cells arranged in a matrix. The first voltage generating circuit generates a first positive voltage. The reference voltage generating circuit generates a first reference voltage. The first voltage control circuit sets the first positive voltage at a voltage value based on the first reference voltage and outputs a resulting second positive voltage. An output impedance of the first voltage control circuit varies depending on the number of bits into which data is simultaneously written. The second positive voltage is used to write and erase data into and from the memory cells.

REFERENCES:
patent: 5369354 (1994-11-01), Mori
patent: 6219293 (2001-04-01), Butler et al.
patent: 6535435 (2003-03-01), Tanaka et al.
Shigeru Atsumi, et al., “A Channel-Erasing 1.8-V-Only 32-Mb NOR Flash EEPROM with a Bitline Direct Sensing Scheme”, IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000, pp. 1648-1654.
Wei-Hua Liu, et al., “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications”, NVSMW 4.1, Feb. 1997, pp. 1-3.

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