Read/verify circuit for multilevel memory cells with ramp...

Details Read/verify circuit for multilevel memory cells with ramp... Read/verify circuit for multilevel memory cells with ramp...

2008-07-08

2008-07-08

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200, C365S185210, C365S185030, C365S185190

Reexamination Certificate

active

07397702

ABSTRACT:
A read/verify circuit for multilevel memory cells includes: a read terminal selectively connectable to a plurality of array cells, having respective array threshold voltages; a plurality of reference cells, having respective reference threshold voltages; and a plurality of threshold-detection circuits, for detecting the array thresholds and the reference thresholds. In particular, the read terminal and the reference cells are each connected to a respective threshold-detection circuit. Each threshold-detection circuit is provided with a respective detector element of a resistive type, set so as to be traversed by a current response to turning-on of the respective array cell or reference cell associated thereto.

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