Sample-and-hold circuits having reduced channel conductance...

Details Sample-and-hold circuits having reduced channel conductance... Sample-and-hold circuits having reduced channel conductance...

2008-06-10

2008-06-10

Lam, Tuan T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S093000, C327S094000, C327S095000

Reexamination Certificate

active

07385427

ABSTRACT:
An electronic device, such as a sample-and-hold circuit, includes a field effect transistor (FET), a capacitor, and a voltage offset circuit. The FET is configured to receive a signal at a first terminal thereof and selectively provide the signal to a second terminal thereof responsive to a switching signal at a gate terminal thereof. The capacitor is electrically connected to the second terminal of the FET. The voltage offset circuit is electrically connected to the first terminal and the gate terminal of the FET. The voltage offset circuit is configured to maintain a substantially constant voltage differential between the first terminal and the gate terminal of the FET while the signal is provided to the second terminal of the FET and substantially independent of a voltage level of an input signal. Related methods of operation are also discussed.

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Notice to Submit Response corresponding to Korean Patent Application No. 10-2005-0063902 mailed Oct. 23, 2006.

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