Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2008-06-24
2008-06-24
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C702S118000
Reexamination Certificate
active
07392442
ABSTRACT:
A built-in self-test (BIST) architecture having distributed algorithm interpretation is described. The architecture includes three tiers of abstraction: a centralized BIST controller, a set of sequencers, and a set of memory interfaces. The BIST controller stores a set of commands that generically define an algorithm for testing memory modules without regard to the physical characteristics or timing requirements of the memory modules. The sequencers interpret the commands in accordance with a command protocol and generate sequences of memory operations. The memory interfaces apply the memory operations to the memory module in accordance with physical characteristics of the memory module, e.g., by translating address and data signals based on the row-column arrangement of the memory modules to achieve bit patterns described by the commands. The command protocol allows powerful algorithms to be described in an extremely concise manner that may be applied to memory modules having diverse characteristics.
REFERENCES:
patent: 5224101 (1993-06-01), Popyack, Jr.
patent: 5617531 (1997-04-01), Crouch et al.
patent: 5633877 (1997-05-01), Shephard et al.
patent: 5661732 (1997-08-01), Lo et al.
patent: 5675545 (1997-10-01), Madhavan et al.
patent: 5995731 (1999-11-01), Crouch et al.
patent: 6249889 (2001-06-01), Rajsuman et al.
patent: 6272588 (2001-08-01), Johnston et al.
patent: 6327556 (2001-12-01), Geiger et al.
patent: 6347056 (2002-02-01), Ledford et al.
patent: 6349398 (2002-02-01), Resnick
patent: 6415403 (2002-07-01), Huang et al.
patent: 6643804 (2003-11-01), Aipperspach et al.
patent: 6658611 (2003-12-01), Jun
patent: 6665817 (2003-12-01), Rieken
patent: 6874111 (2005-03-01), Adams et al.
patent: 7184915 (2007-02-01), Hansquine et al.
patent: 2001/0004326 (2001-06-01), Terasaki
patent: 2002/0199139 (2002-12-01), Dortu et al.
patent: 2003/0115521 (2003-06-01), Rajski et al.
patent: 2003/0115525 (2003-06-01), Hill et al.
patent: 2003/0167426 (2003-09-01), Slobodnik
patent: 02075337 (2002-09-01), None
Averbuj Roberto Fabian
Hansquine David W.
Britt Cynthia
Ciccozzi John L.
Pauley Nicholas J.
Qualcomm Incorporated
Rouse Thomas
LandOfFree
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