Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-04
2008-03-04
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07340694
ABSTRACT:
A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.
REFERENCES:
patent: 6148436 (2000-11-01), Wohl
R. Rudell et al., “Espresso-MV Algorithms for Multiple-Valued Logic Minimization”, article, 1985, pp. 230-233, Dept of Electrical Engineering & Computer Science, University of California, Berkeley, CA, USA.
Baumgartner Jason Raymond
Kanzelman Robert Lowell
Mony Hari
Paruthi Viresh
Dillon & Yudell LLP
Do Thuan
International Business Machines - Corporation
Salys Casimer K.
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