Thin film transistor array panel and manufacturing method...

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Field effect device in non-single crystal – or...

Reexamination Certificate

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Reexamination Certificate

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07355206

ABSTRACT:
Gate lines and a gate shorting bar connected to the gate lines, which include lower and upper films, are formed on a substrate. A gate insulating layer, semiconductors, and ohmic contacts are formed in sequence. Data lines and a data shorting bar connected to the data lines, which include lower and upper films, are formed thereon. A passivation layer is formed on the data lines and the data shorting bar. The passivation layer and the gate insulating are patterned to form contact holes exposing the lower films of the gate lines and the data lines. Connecting portions of the gate lines and the data lines for connection with driving circuits are locate opposite the shorting bars with respect to the contact holes.

REFERENCES:
patent: 6013923 (2000-01-01), Huang
patent: 6441401 (2002-08-01), Jung et al.
patent: 6781651 (2004-08-01), Song et al.
patent: 6970209 (2005-11-01), Jun
patent: 11-509938 (1999-08-01), None

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