Coplanar silicon-on-insulator (SOI) regions of different...

Details Coplanar silicon-on-insulator (SOI) regions of different... Coplanar silicon-on-insulator (SOI) regions of different...

2008-07-01

2008-07-01

Ngo, Ngan (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S152000, C438S155000, C257SE21320, C257SE21545, C257SE21561

Reexamination Certificate

active

07393730

ABSTRACT:
In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region having a second crystal orientation and a third SOI region having a third crystal orientation on the substrate. The first, second and third SOI regions are coplanar. Numerous other aspects are provided.

REFERENCES:
patent: 5296410 (1994-03-01), Yang
patent: 5734564 (1998-03-01), Brkovic
patent: 5882987 (1999-03-01), Srikrishnan
patent: 6815278 (2004-11-01), Ieong et al.
patent: 6830962 (2004-12-01), Guarini et al.
patent: 6972478 (2005-12-01), Waite et al.
patent: 6998684 (2006-02-01), Anderson et al.
patent: 7060585 (2006-06-01), Cohen et al.
patent: 7125785 (2006-10-01), Cohen et al.
patent: 7148092 (2006-12-01), Isobe et al.
patent: 2003/0218171 (2003-11-01), Isobe et al.
patent: 2004/0256700 (2004-12-01), Doris
patent: 2005/0082531 (2005-04-01), Rim
patent: 2005/0277260 (2005-12-01), Cohen et al.
patent: 2006/0024931 (2006-02-01), Chan et al.
patent: 2006/0073646 (2006-04-01), Yang
patent: 2006/0113605 (2006-06-01), Currie
patent: 2006/0170045 (2006-08-01), Yam et al.
patent: 2006/0231893 (2006-10-01), Bernstein et al.
patent: 2006/0272574 (2006-12-01), Waite et al.
patent: 2007/0015346 (2007-01-01), Cohen et al.
Melanie J. Sherony et al., “Minimization of Threshold Voltage Variation in SOI MOSFETs”, Proceedings 1994 IEEE International SOI Conference, Oct. 1994, pp. 131-132.
J. A. Manderlrnan et al., “Floating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)”, Proceedings 1996 IEEE International SOI Conference, Oct. 1996, pp. 136-137.
R. Islam et al., “Wafer Level Packaging and 3D Interconnect for JC Technology”, 2002 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 212-217.
N. Sato et al., “Precise Thickness Control for Ultra-Thin SOI in ELTRAN® SOI-EpiTHWafer”, 2002 IEEE International SOI Conference, Oct. 2002, pp. 209-210.
A. Vandooren et al., “Scaling Assessment of Fully-Depleted SOI Technology at the 30nm Gate Length Generation”, 2002 IEEE International SOI Conference, Oct. 2002, pp. 25-27.
P. Lindner et al., “3D Interconnect through Aligned Wafer Level Bonding”, 2002 Electronic Components and Technology Conference, pp. 1439-1443.
M. Yang et al., “High Performance CMOS Fabricated on Hybrid Substrate with Differenct Crystal Orientations”, 2003 IEEE, pp. 18.7.1-18.7.4.
M. Yang et al., “On the Integration of CMOS with Hybrid Crystal Orientations”, 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 160-161.
Akiko Ohata et al., “Mobility Issues in Ultra-Thin SOI MOSFETs: Thickness Variations, GIFBE and Coupling Effects”, 2004 IEEE, pp. 109-112.
Toshinori Numata, “Device Design for Subthreshold Slope and Threshold Voltage Control in Sub- 100-nm Fully Depleted SOI MOSFETs”, IEEE Transactions on Electron Devices, vol. 51, No. 12, Dec. 2004, pp. 2161-2167.
Sixto Ortiz Jr., http://www.processor.com/Editorial/article.asp?article=articles/p2548/31p48.asp&g..., IBM Extends Silicon with SSDOI, published Nov. 28, 2003, vol. 25, Issue 48.

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