Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
2008-04-15
2008-04-15
Sough, Hyung S. (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
C711S202000, C711S204000, C711S207000, C711S213000, C711S214000
Reexamination Certificate
active
07360058
ABSTRACT:
Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.
REFERENCES:
patent: 5335333 (1994-08-01), Hinton et al.
patent: 5924128 (1999-07-01), Luick et al.
patent: 6374342 (2002-04-01), Sasahara
Flood Rachel Marie
Frommer Scott Bruce
Hrusecky David Allen
Levenstein Sheldon B.
Vaden Michael Thomas
Gerhardt Diana R.
Glanzman Gerald H.
International Business Machines - Corporation
Patel Kaushikkumar
Sough Hyung S.
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