Method and circuit for compressing test data in a memory device

Details Method and circuit for compressing test data in a memory device Method and circuit for compressing test data in a memory device

1998-05-22

2000-12-19

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

365201, G11C 2900

Patent

active

061638633

ABSTRACT:
A test circuit in a memory device includes test data read paths and test data write paths for performing data compression to more quickly test the memory cells in the memory device. The memory device includes first and second banks of memory cells having a redundancy plane defined between the two banks and including at least one data terminal. The test circuit includes a test mode terminal adapted to receive a test mode signal, and a test data write path coupled to a plurality of memory cells in the first and second banks. The test circuit further includes a first test data read path coupled to a plurality of memory cells in the first bank, and a second test data read path coupled to a plurality of memory cells in the second bank. A test data write circuit is coupled to the data terminal and to the test data write path and transfers test data placed on the data terminal over the test data write path to a plurality of memory cells in the first and second banks. A test data read circuit is coupled to the first and second test data read paths. The test data read circuit drives a first error signal active when data on the first test data read path is different from predetermined binary values. The test data read circuit drives a second error signal active when the data on the second test data read path is different from predetermined binary values.

REFERENCES:
patent: 5913928 (1999-06-01), Morzano
patent: 5936901 (1999-08-01), Wong et al.
patent: 5999450 (1999-12-01), Dallabora et al.
patent: 6002620 (1999-12-01), Tran et al.
patent: 6018811 (2000-01-01), Merritt
patent: 6032274 (2000-02-01), Manning

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