High-voltage NMOS-transistor and associated production method

Details High-voltage NMOS-transistor and associated production method High-voltage NMOS-transistor and associated production method

2011-03-01

2011-03-01

Le, Thao X (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29031, C438S400000

Reexamination Certificate

active

07898030

ABSTRACT:
An n-conductively doped source region (2) in a deep p-conducting well (DP), a channel region (13), a drift region (14) formed by a counterdoping region (12), preferably below a gate field plate (6) insulated by a gate field oxide (8), and an n-conductively doped drain region (3) arranged in a deep n-conducting well (DN) are arranged in this order at a top side of a substrate (1). A lateral junction (11) between the deep p-conducting well (DP) and the deep n-conducting well (DN) is present in the drift path (14) in the vicinity of the drain region (3) so as to avoid a high voltage drop in the channel region (13) during the operation of the transistor and to achieve a high threshold voltage and also a high breakdown voltage between source and drain.

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