Semiconductor memory device having memory cells designed to offs

Details Semiconductor memory device having memory cells designed to offs Semiconductor memory device having memory cells designed to offs

1996-01-29

1998-09-01

Zarabian, A.

Static information storage and retrieval

Systems using particular element

Capacitors

365210, 365 63, G11C 1124

Patent

active

058019839

ABSTRACT:
A semiconductor memory such as a dynamic random access memory (DRAM) has its memory cells designed to offset the effects of parasitic capacitance along the bit lines. In one embodiment, the bit storage capacitors of one group of memory cells has a capacitance value that is selected to be different from the capacitance value of the bit storage capacitors in a second group of memory cells. In a preferred embodiment, the capacitance value of a given bit storage capacitor is selected as a function of the distance of the associated memory cell from the sense amplifier, as measured along the bit line.

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