System, method and computer program product for designing...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07353476

ABSTRACT:
A system for designing connecting terminals of a semiconductor device, having a power supply cell arranging unit configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip, an I/O signal cell arranging unit configured to arrange I/O signal cells at some of the I/O slots where the power supply cells are not arranged, a first connecting net generator configured to generate a first connecting net connecting the I/O slots to bumps formed on the semiconductor chip, a second connecting net generator configured to generate a second connecting net connecting the bumps to external electrodes formed on a package base, and a verifier configured to verify whether the power supply cells, I/O signal cells, and first and second connecting nets violate predetermined design rules.

REFERENCES:
patent: 5885855 (1999-03-01), Liang
patent: 08-110918 (1996-04-01), None
patent: 09-325979 (1997-12-01), None
patent: 2001-060625 (2001-03-01), None

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