Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-08-30
2011-08-30
Gu, Shawn X (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S114000, C711S130000, C711S133000, C711S144000
Reexamination Certificate
active
08010750
ABSTRACT:
A network on chip (‘NOC’) including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive.
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Comparan Miguel
Hoover Russell D.
Kuesel Jamie R.
Mejdrich Eric O.
Biggers & Ohanian LLP
Gu Shawn X
International Business Machines - Corporation
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