Hardware recovery in a multi-threaded architecture

Details Hardware recovery in a multi-threaded architecture Hardware recovery in a multi-threaded architecture

2008-05-13

2008-05-13

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S015000

Reexamination Certificate

active

07373548

ABSTRACT:
Log-based hardware recovery. A checkpointed state of a system includes both architectural register values and memory. The checkpoint consists of a copy of the architectural register file values at the time the checkpoint is generated. An ordered log of non-deterministic events is maintained so that the responses can be repeated to simulate a complete checkpoint for error recovery purposes. When a processor detects an error, the processor reloads the state from the last checkpoint and repeats the non-deterministic events from the log.

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