Semiconductor memory device having advanced test mode

Details Semiconductor memory device having advanced test mode Semiconductor memory device having advanced test mode

2008-01-22

2008-01-22

Iqbal, Nadeem (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

07321991

ABSTRACT:
An apparatus for testing an operation of a semiconductor memory device having a plurality of banks in a compress test mode includes an internal address generator for receiving an external bank address and generating internal bank addresses in response to a bank interleaving test signal; a read operation testing block for receiving the internal bank addresses and testing a read operation of the semiconductor memory device in response to the bank interleaving test signal; and a write operation testing block for receiving the internal bank addresses and testing a write operation of the semiconductor memory device.

REFERENCES:
patent: 5587950 (1996-12-01), Sawada et al.
patent: 5959930 (1999-09-01), Sakurai
patent: 6529429 (2003-03-01), Cowles et al.
patent: 6721230 (2004-04-01), Weitz
patent: 2003/0099142 (2003-05-01), Cowles et al.
patent: 2003/0142577 (2003-07-01), Kumazaki et al.

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