Self-alignment for semiconductor patterns

Details Self-alignment for semiconductor patterns Self-alignment for semiconductor patterns

2011-03-08

2011-03-08

Nhu, David (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S774000, C257SE21320, C257SE21231, C257SE21304, C257SE21545, C257SE21548, C257SE21585

Reexamination Certificate

active

07902613

ABSTRACT:
Various systems and methods related to semiconductor devices having a plurality of layers and having a first conductive trace on a first layer electrically connected to a second conductive trace on a second layer and electrically isolated from a third electrical trace on the second layer are provided. A semiconductor structure can include first, second and third layers. The first conducting layer may be etched to form a first trench for the first conductive trace. A layer of material on the second layer in the first trench can define a patch area, wherein the patch area is disposed in a location where the first trench crosses over the third electrical trace. A second trench may be etched in an area defined by the first trench and the patch area to remove material in the second layer exposed by the first trench, leaving material of the layer under the patch area.

REFERENCES:
patent: 5534877 (1996-07-01), Sorbello et al.
patent: 6008763 (1999-12-01), Nystrom et al.
patent: 6054953 (2000-04-01), Lindmark
patent: 6288679 (2001-09-01), Fischer et al.

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