Method of manufacturing a semiconductor integrated circuit...

Details Method of manufacturing a semiconductor integrated circuit... Method of manufacturing a semiconductor integrated circuit...

2011-03-15

2011-03-15

Tran, Thien F (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S153000, C438S154000, C438S479000, C438S517000

Reissue Patent

active

RE042223

ABSTRACT:
Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation. A method of the present invention includes the steps of: forming and patterning a LOCOS reaching an embedded insulating film, a gate oxide film, a well and a polysilicon film serving as a gate electrode; forming a second conductivity type high-density impurity region in an ultra-shallow portion of each of a source region and a drain region, a second conductivity type impurity region having a low density under the second conductivity type high-density impurity region of the ultra-shallow portion, and a second conductivity type impurity region having a high density under the second conductivity type impurity region having a low density and above the embedded insulating film; forming a sidewall around the gate electrode; forming a second conductivity type impurity region in each of the source region and the drain region; forming an interlayer insulating film and forming contact holes in the source region, the drain region and the gate electrode; and forming a wiring on the interlayer insulating film.

REFERENCES:
patent: 5719425 (1998-02-01), Akram et al.
patent: 6333540 (2001-12-01), Shiozawa et al.
patent: 6433391 (2002-08-01), En et al.
patent: 7253048 (2007-08-01), Wake et al.
patent: 2002/0005553 (2002-01-01), Ootsuka et al.

Affiliated with

Also associated with

Rating

Method of manufacturing a semiconductor integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing a semiconductor integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor integrated circuit... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2747320