Data cipher processors

Details Data cipher processors Data cipher processors

2011-06-21

2011-06-21

Colin, Carl (Department: 2493)

Cryptography

Particular algorithmic function encoding

C380S037000, C380S277000

Reexamination Certificate

active

07965836

ABSTRACT:
Data cipher processors, advanced encryption standard (AES) cipher system, and AES cipher methods using a masking method perform round operations using a round key, a plain text, a cipher text, and masking data. Some of the round operations are implemented over a composite Galois Field GF(•). Original data and predetermined masking data are processed according to a predetermined rule. Sub-byte transformation operations used in the cipher method and system may include an affine transformation, an inverse affine transformation, an isomorphic transformation, and an inverse isomorphic transformation which are linear transformations, and an inverse transformation that is a non-linear transformation.

REFERENCES:
patent: 6542553 (2003-04-01), Le Dantec et al.
patent: 6574772 (2003-06-01), Chou
patent: 6611512 (2003-08-01), Burns
patent: 6940975 (2005-09-01), Kawamura et al.
patent: 7158638 (2007-01-01), Okada et al.
patent: 7257229 (2007-08-01), Leshem
patent: 7295671 (2007-11-01), Snell
patent: 2002/0012430 (2002-01-01), Lim
patent: 2002/0191784 (2002-12-01), Yup et al.
patent: 2003/0055858 (2003-03-01), Dubey et al.
patent: 2003/0093450 (2003-05-01), Chen
patent: 2003/0099352 (2003-05-01), Lu et al.
patent: 2003/0108195 (2003-06-01), Okada et al.
patent: 2003/0133568 (2003-07-01), Stein et al.
patent: 2004/0078409 (2004-04-01), Stein et al.
patent: 2005/0283714 (2005-12-01), Korkishko et al.
patent: 2006/0120527 (2006-06-01), Baek
patent: 2006/0198524 (2006-09-01), Sexton
patent: 1 267 514 (2002-12-01), None
patent: 1 557 740 (2005-07-01), None
patent: 2002-366029 (2002-12-01), None
patent: 2003015522 (2003-01-01), None
patent: 1020030051111 (2003-06-01), None
patent: WO 03/019357 (2003-03-01), None
patent: WO 03/101020 (2003-12-01), None
patent: WO 2004/014016 (2004-02-01), None
Elena Trichina; “Logic Design for AES SubByte Transformation on Masked Data”; Cryptology ePrint Archive, 2003/236, (2003); “http://eprint.iacr.org/2003/236.pdf”; pp. 1-13.
Christof Paar, Peter Fleischmann, Peter Roelse; “Efficient multiplier architectures for galois fields GF(2 4n)”; IEEE, 1998; 22 Pages.
Trichina et al; “Supplemental Cryptographic Hardware for Smart Cards”; IEEE Nov.-Dec. 2001; pp. 26-35.
Satoh et al “A Compact Rijndael Hardware Architecture with S-Box Optimization” ASIACRYPT 2001, LNCS 2248; 2001 pp. 239-254.
Jovan Dj. Golic and Christophe Tymen; “Multiplicative Masking and Power Analysis of AES”; Oct. 30-31, 2001; pp. 1-14.
Daemen et al., “Rijndael: beyond the AES”, Mikulasska kryptobesidka, 2002, 1 page.
Golic et al., “Multiplicative Masking and Power Analysis of AES”,Cryptographic Hardware and Embedded Systems—CHES 2002, vol. 2523 ofLecture Notes in Computer Science, pp. 198-212, Springer-Verlag, 2003.
Notice to Submit a Response for Korean Patent Application No. 10-2004-0017671 mailed on Feb. 27, 2006.
Daemen et al. “AES Proposal: Rijndael” 45pages (1999).
Daemen et al., “Rijndael: beyond the AES”, Mikulasska kryptobesidka, pp. 1-10 (2002).
Baek et al. “DPA-Resistant Finite Field Multipliers and Secure AES Design”, LNCS, Information Security Practice and Experience, 2006, vol. 3903, p. 1-12.
Chang et al. “Securing AES against Second-Order DPA by Simple Fixed-Value Masking”, vol. 2003, No. 15, p. 145-150.
First Office Action dated Dec. 21, 2010 corresponding to Japanese Patent Application No. 2005-075869, 4 pages.
Golic et al. “Universal masking on logic gate level”,Electronics Letters, [online] Apr. 29, 2004; vol. 40, Issue 9, p. 526-528, URL, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1296970.
Ogino et al., (DES) AES (Rijndael) (2), Jul. 2001, p. 56-60.
Oswald et al. SCA-Lab Technical Report Series: “Secure and Efficient Masking of AES—A Mission Impossible?”, Cryptology e Print Archive: Report 2004/134, [online], Version: 20040604:121931, p. 1-18, URL, http://eprint.iacr.org/2004/134.pdf.
Trichina, Elena Cominational Logic Design for AES Subbyte Transformation on Masked Data, Cryptology ePrint Archive: Report 2003/236, [online], Version 20031112: 135420, pp. 1-13, URL, http://eprint.iacr.org/2003/236.pdf.

Affiliated with

Also associated with

Rating

Data cipher processors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data cipher processors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data cipher processors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2742295