Semiconductor memory device with memory cells operated by...

Details Semiconductor memory device with memory cells operated by... Semiconductor memory device with memory cells operated by...

2008-07-08

2008-07-08

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S226000, C365S227000, C257S903000

Reexamination Certificate

active

07397693

ABSTRACT:
A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

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patent: 9-185886 (1997-07-01), None
patent: 2001-28401 (2001-01-01), None

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