Debugging system, debugging circuit and information...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C714S042000

Reexamination Certificate

active

07873875

ABSTRACT:
A debugging system includes a CPU that is a debugging target and a debugging circuit. The CPU has an output part configured to independently output stack access information of a stack access and data access information of a data access excluding the stack access, as data access information of the CPU that is monitored by the debugging circuit. The debugging circuit has a trace part configured to independently generate and output trace information of the stack access from the stack access information that is output from the CPU and trace information of the data access excluding the stack access from the data access information that is output from the CPU.

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patent: 6438715 (2002-08-01), Assouad
patent: 6745351 (2004-06-01), Mastro
patent: 2003/0061550 (2003-03-01), Ng et al.
patent: 2004/0064763 (2004-04-01), Swoboda
patent: 2005/0268177 (2005-12-01), John
patent: 2007/0220360 (2007-09-01), Weinert et al.
patent: 2007/0260435 (2007-11-01), Matsunaga et al.
patent: 2004-038981 (2004-02-01), None
patent: 2004-178591 (2004-06-01), None

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