Bitcell simulation device and methods

Details Bitcell simulation device and methods Bitcell simulation device and methods

2011-04-26

2011-04-26

Frejd, Russell (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S002000, C702S057000, C702S179000

Reexamination Certificate

active

07933760

ABSTRACT:
A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.

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Calhoun et al., Static Noise Margin Variation for Sub-Threshold SRAM in 65-nm CMOS, IEEE Journal of Solid-State Circuits, vol. 41, No. 7, Jul. 2006, pp. 1673-1679.

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