Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-11
2011-01-11
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07870514
ABSTRACT:
A method of designing a pattern of a hole pattern having a configuration, in which grid of interval smaller than a minimum permissible pitch according to a design rule for a semiconductor integrated circuit is provided in a pattern drawing, a hole pattern is arranged on a first lattice point which is an intersection of the grid, and, at the same time, other hole patterns are not arranged on a second lattice point group which is on the periphery of the first lattice point, and is adjacent to the first lattice point is provided. And, the number of hole patterns, which may be arranged in a third lattice point group of a plurality of lattice points which are on the periphery of a second lattice point group and are within a predetermined distance from the first lattice point, is controlled.
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Chiang Jack
Parihar Suchin
Renesas Electronics Corporation
Young & Thompson
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