Method of designing a pattern

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07870514

ABSTRACT:
A method of designing a pattern of a hole pattern having a configuration, in which grid of interval smaller than a minimum permissible pitch according to a design rule for a semiconductor integrated circuit is provided in a pattern drawing, a hole pattern is arranged on a first lattice point which is an intersection of the grid, and, at the same time, other hole patterns are not arranged on a second lattice point group which is on the periphery of the first lattice point, and is adjacent to the first lattice point is provided. And, the number of hole patterns, which may be arranged in a third lattice point group of a plurality of lattice points which are on the periphery of a second lattice point group and are within a predetermined distance from the first lattice point, is controlled.

REFERENCES:
patent: 6893801 (2005-05-01), Inoue et al.
patent: 7376931 (2008-05-01), Kokubun
patent: 7399558 (2008-07-01), Yamazoe et al.
patent: 2003/0152873 (2003-08-01), Tainaka et al.
patent: 2004/0166422 (2004-08-01), Yamazoe et al.
patent: 2005/0138598 (2005-06-01), Kokubun
patent: 2005/0142454 (2005-06-01), Fujimoto et al.
patent: 2005-183793 (2005-07-01), None
patent: 2005-189683 (2005-07-01), None

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