Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2011-07-05
2011-07-05
Nguyen, Thanh (Department: 2893)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S459000, C257SE29241
Reexamination Certificate
active
07972910
ABSTRACT:
It is an object of the present invention to improve a factor which influences productivity such as variation caused by a characteristic defect of a circuit by thinning or production yield when an integrated circuit device in which a substrate is thinned is manufactured. A stopper layer is formed over one surface of a substrate, and an element is formed over the stopper layer, and then, the substrate is thinned from the other surface thereof. A method in which a substrate is ground or polished or a method in which the substrate is etched by chemical reaction is used as a method for thinning or removing the substrate.
REFERENCES:
patent: 4838654 (1989-06-01), Hamaguchi et al.
patent: 5391257 (1995-02-01), Sullivan et al.
patent: 5834327 (1998-11-01), Yamazaki et al.
patent: 6100166 (2000-08-01), Sakaguchi et al.
patent: 6127199 (2000-10-01), Inoue et al.
patent: 6372608 (2002-04-01), Shimoda et al.
patent: 6534382 (2003-03-01), Sakaguchi et al.
patent: 6645830 (2003-11-01), Shimoda et al.
patent: 6646711 (2003-11-01), Sugano
patent: RE38466 (2004-03-01), Inoue et al.
patent: 6700631 (2004-03-01), Inoue et al.
patent: 6818530 (2004-11-01), Shimoda et al.
patent: 6885389 (2005-04-01), Inoue et al.
patent: 2002/0032073 (2002-03-01), Rogers et al.
patent: 2002/0067459 (2002-06-01), Sugano
patent: 2002/0146893 (2002-10-01), Shimoda et al.
patent: 2003/0008437 (2003-01-01), Inoue et al.
patent: 2003/0032210 (2003-02-01), Takayama et al.
patent: 2003/0082889 (2003-05-01), Maruyama et al.
patent: 2003/0174275 (2003-09-01), Asano et al.
patent: 2003/0203547 (2003-10-01), Sakaguchi et al.
patent: 2003/0217805 (2003-11-01), Takayama et al.
patent: 2003/0224582 (2003-12-01), Shimoda et al.
patent: 2004/0027055 (2004-02-01), Yamazaki et al.
patent: 2004/0129960 (2004-07-01), Maruyama et al.
patent: 2004/0164302 (2004-08-01), Arai et al.
patent: 2004/0219762 (2004-11-01), Shimoda et al.
patent: 2004/0239827 (2004-12-01), Yamazaki et al.
patent: 2006/0030122 (2006-02-01), Shimoda et al.
patent: 2006/0057836 (2006-03-01), Nagarajan et al.
patent: 01-181570 (1989-07-01), None
patent: 02-154232 (1990-06-01), None
patent: 04-170520 (1992-06-01), None
patent: 04-178633 (1992-06-01), None
patent: 04-299859 (1992-10-01), None
patent: 05-218365 (1993-08-01), None
patent: 06-291291 (1994-10-01), None
patent: 09-105896 (1997-04-01), None
patent: 2000-241822 (2000-09-01), None
patent: 2000-248243 (2000-09-01), None
patent: 2001-125138 (2001-05-01), None
patent: 2001-247827 (2001-09-01), None
patent: 2002-031818 (2002-01-01), None
patent: 2002-033464 (2002-01-01), None
patent: 2002-087844 (2002-03-01), None
patent: 2002-217391 (2002-08-01), None
patent: 2004-214281 (2004-07-01), None
patent: 2004-282050 (2004-10-01), None
patent: WO 2006/006611 (2006-01-01), None
patent: WO 2006/011664 (2006-02-01), None
Dairiki Koji
Kusumoto Naoto
Tsurume Takuya
Nguyen Thanh
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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