System and method for power domain isolation

Details System and method for power domain isolation System and method for power domain isolation

2011-07-19

2011-07-19

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S063000, C326S021000

Reexamination Certificate

active

07982498

ABSTRACT:
In one embodiment, a power domain isolation interface is disclosed. The interface has a level shifter having a signal input coupled to a first power domain and a memory element. The memory element has a signal input coupled to an output of the level shifter, an output coupled to a second power domain, and a hold enable input, wherein the memory element is configured to hold an input state when the hold enable input becomes asserted.

REFERENCES:
patent: 7251740 (2007-07-01), Newman
Chattopadhyay, A., et al., “Automatic ADL-based Operand Isolation for Embedded Processors,” Proceedings of the Design Automation and Test in Europe Conference, Mar. 10, 2006, 6 pages, vol. 1.
Zhang, G., et al., “Low Power Techniques on a High Speed Floating-point Adder Design,” Proceedings of the 2007 IEEE Inernational Conference on Integration Technology, Mar. 20-24, 2007, pp. 241-244. Shenzhen, China.

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