Protection of user-level applications based on page table...

Details Protection of user-level applications based on page table... Protection of user-level applications based on page table...

2011-03-29

2011-03-29

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S163000, C711SE12014

Reexamination Certificate

active

07917724

ABSTRACT:
In one embodiment, the present invention includes a virtual machine monitor (VMM) to access a protection indicator of a page table entry (PTE) of a page of a set of memory buffers and determine a state of the protection indicator, and if the protection indicator indicates that the page is a user-level page and if certain information of an agent that seeks to use the page matches that in a protected memory address array, a page table base register (PTBR) is updated to a protected page table (PPT) base address. Other embodiments are described and claimed.

REFERENCES:
patent: 6986006 (2006-01-01), Willman et al.
patent: 2007/0005992 (2007-01-01), Schlussler et al.
patent: 2007/0006175 (2007-01-01), Durham et al.
patent: 2007/0156999 (2007-07-01), Durham et al.

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