Storage nitride encapsulation for non-planar sonos NAND...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S196000, C438S218000, C438S221000, C438S294000, C438S404000, C257S093000, C257S374000, C257S446000, C257S501000, C257S506000

Reexamination Certificate

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07910453

ABSTRACT:
The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.

REFERENCES:
patent: 6599824 (2003-07-01), Krivokapic
patent: 2005/0139952 (2005-06-01), Koh
patent: 2007/0287245 (2007-12-01), Hieda et al.
patent: 2008/0087941 (2008-04-01), Yun et al.
patent: 2008/0160695 (2008-07-01), Shin
patent: 1697155 (2005-11-01), None
Chinese Patent Office, Office Action of Apr. 13, 2010, Application No. 200910000109.4, 5 pages.

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