Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-04-16
2000-12-19
Loke, Steven H.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257316, 36518501, 36518517, H01L 29788, G11C 1604
Patent
active
061630489
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to improvements in semiconductor memories and, more particularly, to improvements in electrically erasable, electrically programmable read-only memories used for large capacity data storage.
2. Description of the Related Art
The demand for portable and hand held devices which require large amounts of data storage has grown substantially within recent years and is expected to continue to grow well into the next decade. Products such as digital cameras, cellular telephones, personal organizers, voice recording devices and palm top personal computers as well as a host of specialized remote data collection tools are available today and several new products are in development. In nearly all of these products data is stored on solid state electronic media rather than on a hard disk drive, due to the requirements of higher performance, lower energy consumption and superior ruggedness. However, the cost of a given amount of solid state storage media has proven to greatly exceed that of hard disk drive solutions, making it difficult to build attractively priced products which contain enough solid state memory to adequately meet the product requirements.
Recently, a "NAND" type non-volatile memory cell structure has reemerged as a proposed way to reduce manufacturing costs over conventional solid state storage. Higher storage capacity and lower costs are achieved by utilizing a smaller memory cell composed of a single memory transistor which shares each of its nodes with adjacent memory cells. Several such cells are grouped together in a "NAND stack", with their channels in series, along with means to connect the stack ends to a bit line and a reference line. In the past the non-volatile memory transistor used a MNOS non-volatile element, but more recently, floating gate approaches have dominated. In either case the small cell size is the key element which enables higher densities and lower costs.
However, floating gate NAND cells have not been able to realize expected cost reductions due to inherent limitations. Internal write voltages of floating gate NAND memories are typically five to seven times the normal CMOS product power supply limits. Cell sizes are difficult to scale due to the stacked polysilicon floating gate geometry making manufacturing increasingly difficult. Threshold voltages are difficult to control, causing long test times and lower product yields. Each of these factors are intrinsic to the floating gate NAND approach and each significantly affects the product cost.
In the past MNOS (Metal Nitride Oxide Silicon) NAND memory arrays were proposed as a means to realize lower costs. The MNOS structure is conceptually a better approach than the floating gate method, since it is simpler to manufacture, has a naturally tighter threshold voltage distribution, requires minimal test times, and enables much lower write voltages. However, the methods proposed for reading and writing MNOS NAND memories progressively weakens the stored data, destroying it altogether prior to the expected life of the product. This problem is referred to as a "disturb".
Referring now to FIG. 1, current NAND technologies utilize a single transistor floating gate device 10. The drain (D), gate (G), source (S), and bulk (B) contacts, as well as the floating gate (FG) are labeled. Current flows in a channel region between the drain and source when the drain and source are at different potentials, and under direct control of the potential placed on the gate relative to the source and bulk, whose potentials need not be equal. The FG is a non-volatile charge storage node isolated from and between the gate and the channel region. To erase a memory cell, a large negative gate to bulk potential is formed that couples the layer FG to a negative potential, causing holes to be accumulated in the channel region. These holes can tunnel to the FG by the Fowler-Nordheim effect, because of the large electric fields that result from the large gate to bulk potentia
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patent: Re35838 (1998-07-01), Momodomi et al.
patent: 5345418 (1994-09-01), Challa
patent: 5349222 (1994-09-01), Shimoji
patent: 5589700 (1996-12-01), Nakao
Hirose Ryan T.
Lancaster Loren T.
Cypress Semiconductor Corporation
Loke Steven H.
Sako Bradley T.
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