Noise filter circuit, dead time circuit, delay circuit,...

Details Noise filter circuit, dead time circuit, delay circuit,... Noise filter circuit, dead time circuit, delay circuit,...

2011-01-18

2011-01-18

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S021000, C327S210000, C327S217000

Reexamination Certificate

active

07872491

ABSTRACT:
A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a signal based on a signal output from the second inverter circuit as a set signal and a reset signal. Each of the first inverter circuit and the second inverter circuit includes a first-conductivity-type transistor and a second-conductivity-type transistor, the capability of one of the first-conductivity-type transistor and the second-conductivity-type transistor being lower than the capability of the other of the first-conductivity-type transistor and the second-conductivity-type transistor.

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U.S. Appl. No. 12/172,690, filed Jul. 14, 2008 in the name of Saito.

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