Tri-state I/O port

Details Tri-state I/O port Tri-state I/O port

2011-01-04

2011-01-04

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S083000, C326S086000, C327S108000, C327S112000

Reexamination Certificate

active

07863933

ABSTRACT:
The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of the tri-state I/O block is pulled high when the data is high while the output terminal is pulled low when the data is low. The input terminal and the output terminal of the weak buffer are connected to the output terminal of the tri-state logic block. And the input terminal of the delay block is connected to the output terminal of the tri-state logic block while the output terminal of the delay block is fed back to the tri-state logic block. When the output terminal of the tri-state logic block is low to high/high to low, the weak buffer is active and maintains the output terminal of the tri-state logic block weak high/low while the delay block turns off the pull high/low function of the tri-state logic block.

REFERENCES:
patent: 5831449 (1998-11-01), Shigehara et al.
patent: 5864244 (1999-01-01), Kaplinsky
patent: 6707325 (2004-03-01), Taguchi et al.
patent: 7142017 (2006-11-01), Chen
patent: 7362145 (2008-04-01), Takemura et al.
patent: 7375555 (2008-05-01), Wang et al.

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