Multiple source-single drain field effect semiconductor...

Details Multiple source-single drain field effect semiconductor... Multiple source-single drain field effect semiconductor...

2011-04-26

2011-04-26

Bryant, Kiesha R (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29264, C327S237000, C327S281000

Reexamination Certificate

active

07932552

ABSTRACT:
Disclosed are embodiments of a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.

REFERENCES:
patent: 3731122 (1973-05-01), Rosenbaum et al.
patent: 3898479 (1975-08-01), Proebsting
patent: 4500800 (1985-02-01), Cases et al.
patent: 4596959 (1986-06-01), Kawakami
patent: 4629993 (1986-12-01), Bouvier et al.
patent: 4638190 (1987-01-01), Hwang et al.
patent: 4691302 (1987-09-01), Mattausch
patent: 4994773 (1991-02-01), Chen et al.
patent: 5012143 (1991-04-01), Boudewijns
patent: 5111085 (1992-05-01), Stewart
patent: 5121014 (1992-06-01), Huang
patent: 5144174 (1992-09-01), Murakami
patent: 5146306 (1992-09-01), Ferry et al.
patent: 5218237 (1993-06-01), Mao
patent: 5227679 (1993-07-01), Woo
patent: 5268323 (1993-12-01), Fischer et al.
patent: 5334891 (1994-08-01), Marbot
patent: 5400370 (1995-03-01), Guo
patent: 5451894 (1995-09-01), Guo
patent: 5548237 (1996-08-01), Iadanza et al.
patent: 5550728 (1996-08-01), Eillis
patent: 5637900 (1997-06-01), Ker et al.
patent: 5663670 (1997-09-01), Iadanza et al.
patent: 5714784 (1998-02-01), Ker et al.
patent: 5717622 (1998-02-01), Kawamoto et al.
patent: 5754380 (1998-05-01), Ker et al.
patent: 5764093 (1998-06-01), Hayashi et al.
patent: 5770960 (1998-06-01), Iadanza et al.
patent: 5815009 (1998-09-01), Iadanza et al.
patent: 5852315 (1998-12-01), Ker et al.
patent: 5877713 (1999-03-01), Marie
patent: 5894239 (1999-04-01), Bonaccio et al.
patent: 5920203 (1999-07-01), Bailey et al.
patent: 6087875 (2000-07-01), Defaxio
patent: 6169438 (2001-01-01), Wu et al.
patent: 6259294 (2001-07-01), Murakami et al.
patent: 6304124 (2001-10-01), Mizuno
patent: 6320480 (2001-11-01), Kintis et al.
patent: 6429710 (2002-08-01), Ting et al.
patent: 6593789 (2003-07-01), Atallah et al.
patent: 6680636 (2004-01-01), Perry et al.
patent: 6747504 (2004-06-01), Simpson et al.
patent: 6859082 (2005-02-01), Tang
patent: 6867716 (2005-03-01), Zhang
patent: 7030426 (2006-04-01), Neidig
patent: 7034577 (2006-04-01), Kawasumi
patent: 7036098 (2006-04-01), Eleyan et al.
patent: 7124385 (2006-10-01), McGuinness et al.
patent: 7161394 (2007-01-01), Lee
patent: 7180352 (2007-02-01), Mooney et al.
patent: 7212055 (2007-05-01), Yoo et al.
patent: 7403055 (2008-07-01), Minzoni et al.
patent: 7456665 (2008-11-01), Hinz et al.
patent: 7498859 (2009-03-01), Kim
patent: 7525077 (2009-04-01), Kim et al.
patent: 2002/0079925 (2002-06-01), Dietrich et al.
patent: 2002/0140484 (2002-10-01), Komura et al.
patent: 2003/0001650 (2003-01-01), Cao et al.
patent: 2004/0075481 (2004-04-01), Reuveni et al.
patent: 2004/0078768 (2004-04-01), McGuinness et al.
patent: 2004/0090254 (2004-05-01), Owens et al.
patent: 2007/0103215 (2007-05-01), Boerstler et al.
patent: 2007/0115035 (2007-05-01), Hinz et al.
patent: 2007/0247203 (2007-10-01), Cho et al.
patent: 2007/0247205 (2007-10-01), Kim
Abadeer et al., U.S. Appl. No. 11/873,515, Office Action Communication, Feb. 26, 2010, 9 pages.
Baker, et al., “A Waffle Layout Technique Strengthens the ESD Hardness of the NMOS Output Transistor,” 1989 EOS/ESD Symposium Proceedings, pp. 175-181.
Hastings, A., “The Art of Analog Layout,” Prentice Hall, Chapter 12, pp. 416-417.
Abadeer et al., U.S. Appl. No. 11/833,567, Office Action Communication, Feb. 26, 2009, 8 pages.
Abadeer et al., U.S. Appl. No. 11/873,515, Notice of Allowance, Jun. 7, 2010, 4 pages.

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