Amorphous silicon gate with mismatched grain-boundary microstruc

Details Amorphous silicon gate with mismatched grain-boundary microstruc Amorphous silicon gate with mismatched grain-boundary microstruc

1999-03-26

2000-12-19

Mulpuri, Savitri

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438305, 438585, 438935, 438283, H01L 213205

Patent

active

06162716&

ABSTRACT:
A method of forming an amorphous-Si (.alpha.-Si) gate with two or more .alpha.-Si layers with mismatched grains. The first embodiment involves forming two or more amorphous silicon layers over the gate dielectric. The amorphous silicon layers are formed insitu (in a reactor chamber without removing the wafer from the chamber). An amorphous silicon layer is deposited by exposing the substrate to a Silicon containing gas (E.g., SiH.sub.4). The Si containing gas flow is stopped. The chamber is pumped down and back filled with an inert gas to remove said silicon containing gas. In the next insitu step, the Si containing gas is restarted thus depositing the next amorphous Si layer. This deposition and purge cycle is repeated the desired number of times to form two or more mismatched .alpha.-Si layers. In the second embodiment, after an .alpha.-Si layer is deposited, the wafer is etched, for example in an HF vapor or wet clean. Then the wafer is returned to the chamber and another .alpha.-Si layer is formed thereover. The multi-layered .alpha.-Si gate is patterned and conventional processing completes the FET device. The .alpha.-Si gate prevents ion channeling to the gate dielectric.

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