Memory test device and memory test method

Details Memory test device and memory test method Memory test device and memory test method

2011-07-12

2011-07-12

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S718000, C714S723000, C365S201000

Reexamination Certificate

active

07979761

ABSTRACT:
A memory test device, including a universal register to conduct an operation by a predetermined universal command language; an extension register having a larger capacity than the universal register and to conduct an operation by a predetermined extension command language; and a controller to write a predetermined test pattern in an external memory using the extension command language, to read the test pattern written in the memory, to determine the identity of the written test pattern and the read test pattern, and to determine a presence of an error in the memory using the universal command language.

REFERENCES:
patent: 6516410 (2003-02-01), Heller
patent: 6807616 (2004-10-01), McGrath et al.
patent: 7325176 (2008-01-01), Larson et al.
patent: 2004/0068679 (2004-04-01), Vellolil et al.
patent: 2005/0149898 (2005-07-01), Hakewill et al.
Sun et al., An Efficient Functional Test for the Massively-Parallel C*RAM Logic-Enhanced Memory Architecture, Nov. 3-5, 2003, IEEE, pp. 475-482.

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