Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2011-07-19
2011-07-19
Deo, Duy-Vu N (Department: 1713)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S197000, C257SE21215
Reexamination Certificate
active
07981803
ABSTRACT:
The present invention relates to a method of forming a micro pattern of a semiconductor device. In the method according to an aspect of the present invention, an etch target layer, a first hard mask layer, and insulating patterns of a lonzenge are formed over a semiconductor substrate. A first auxiliary pattern is formed on the first hard mask layer including the insulating patterns, wherein a contact hole having the same shape as that of the insulating pattern is formed at the center of four adjacent insulating patterns, which form a quadrilateral. A second auxiliary pattern is formed by etching the first auxiliary pattern so that a top surface of the insulating patterns is exposed. The exposed insulating patterns are removed. A first hard mask pattern is formed by etching the first hard mask layer using an etch process employing the second auxiliary pattern as an etch mask. The etch target layer is etched using the first hard mask pattern.
REFERENCES:
patent: 2005/0173750 (2005-08-01), Park
patent: 2006/0246731 (2006-11-01), Nishida
patent: 2007/0155076 (2007-07-01), Kim
patent: 1606797 (2005-04-01), None
patent: 1961410 (2007-05-01), None
patent: 2006-135334 (2006-05-01), None
patent: 1020000052195 (2000-08-01), None
patent: 1020000052195 (2000-08-01), None
patent: 1020060110096 (2006-10-01), None
patent: 1020060110096 (2006-10-01), None
patent: 1020070054297 (2007-05-01), None
patent: 1020070071043 (2007-07-01), None
patent: 10-2008-0029719 (2008-04-01), None
Woo-Yung Jung, et al.,Patterning with Amorphous Carbon Spacer for Expanding the Resolution Limit of Current Lithography Tool, Optical Microlithography XX, 2007, pp. 1-9, vol. 6520, 65201C, Proc. Of SPIE, Hynix Semiconductor Inc., Icheon-si, Republic of Korea and Lam Research Corporation, Fremont, California.
Woo-Yung Jung, et al.,Double Patterning of Contact Array with Carbon Polymer, Optical Microlithography XXI, 2008, pp. 1-10, vol. 6924, 69240C, Proc. Of SPIE, Hynix Semiconductor Inc., Icheon-si, Republic of Korea and Lam Research Corporation, Fremont, California.
Dahimene Mahmoud
Deo Duy-Vu N
Hynix / Semiconductor Inc.
Kilpatrick Townsend & Stockton LLP
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