Partially depleted SOI field effect transistor having a...

Details Partially depleted SOI field effect transistor having a... Partially depleted SOI field effect transistor having a...

2011-04-05

2011-04-05

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S348000

Reexamination Certificate

active

07919812

ABSTRACT:
Source and drain extension regions and source side halo region and drain side halo region are formed in a top semiconductor layer aligned with a gate stack on an SOI substrate. A deep source region and a deep drain region are formed asymmetrically in the top semiconductor layer by an angled ion implantation. The deep source region is offset away from one of the outer edges of the at least spacer to expose the source extension region on the surface of the semiconductor substrate. A source metal semiconductor alloy is formed by reacting a metal layer with portions of the deep source region, the source extension region, and the source side halo region. The source metal semiconductor alloy abuts the remaining portion of the source side halo region, providing a body contact tied to the deep source region to the partially depleted SOI MOSFET.

REFERENCES:
patent: 5587604 (1996-12-01), Machesney et al.
patent: 6177708 (2001-01-01), Kuang et al.
patent: 6340612 (2002-01-01), Noble et al.
patent: 6353245 (2002-03-01), Unnikrishnan
patent: 6596554 (2003-07-01), Unnikrishnan
patent: 6835982 (2004-12-01), Hogyoku
patent: 7138318 (2006-11-01), Wu et al.

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