Chipstack package and manufacturing method thereof

Details Chipstack package and manufacturing method thereof Chipstack package and manufacturing method thereof

2011-07-12

2011-07-12

Tran, Long K (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C436S014000, C436S018000, C436S033000, C436S106000, C436S113000, C438S458000, C438S462000, C438S672000, C438S676000, C438S977000, C257SE21597, C257SE21705, C257SE33011, C257SE25013

Reexamination Certificate

active

07977156

ABSTRACT:
A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.

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