Method for forming a one-transistor memory cell and related...

Details Method for forming a one-transistor memory cell and related... Method for forming a one-transistor memory cell and related...

Filed on

2011-07-05

Date issued

2011-07-05

Examiner

Roman, Angel (Department: 2812)

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Field effect device

SubSubClass

Having insulated electrode

Other Related Categories

C257SE27112, C257SE29273, C257SE21411, C438S149000, C438S151000, C438S157000

Type

Reexamination Certificate

Status

active

Patent number

07973364

Description

ABSTRACT:
According to one exemplary embodiment, a method for fabricating a one-transistor memory cell includes forming an opening by removing a portion of a gate stack of a silicon-on-insulator (SOI) device, where the SOI device is situated over a buried oxide layer. The method further includes forming a bottom gate of the one-transistor memory cell in a bulk substrate underlying the buried oxide layer. The method further includes forming a charge trapping region in the buried oxide layer. The charge trapping region is formed at an interface between a silicon layer underlying the gate stack and the buried oxide layer. The charge trapping region causes the one-transistor memory cell to have an increased sensing margin. The method further includes forming a top gate of the one-transistor memory cell in the opening. Also disclosed is an exemplary one-transistor memory cell fabricated utilizing the exemplary disclosed method.

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patent: 2006/0284236 (2006-12-01), Bhattacharyya
patent: 2007/0128820 (2007-06-01), Majumdar et al.

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