Stacked non-volatile memory device and methods for...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S314000, C257SE29126, C257SE29309, C257SE29316, C438S261000, C438S287000

Reexamination Certificate

active

07977735

ABSTRACT:
A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

REFERENCES:
patent: 4630086 (1986-12-01), Sato et al.
patent: 5286994 (1994-02-01), Ozawa et al.
patent: 5319229 (1994-06-01), Shimoji et al.
patent: 5668029 (1997-09-01), Huang et al.
patent: 5835396 (1998-11-01), Zhang
patent: 5872034 (1999-02-01), Schlais et al.
patent: 5883409 (1999-03-01), Guterman et al.
patent: 5897351 (1999-04-01), Forbes
patent: 5952692 (1999-09-01), Nakazato et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6026026 (2000-02-01), Chan et al.
patent: 6074917 (2000-06-01), Chang et al.
patent: 6169693 (2001-01-01), Chan et al.
patent: 6218700 (2001-04-01), Papadas et al.
patent: 6322903 (2001-11-01), Siniaguine et al.
patent: 6380068 (2002-04-01), Jeng et al.
patent: 6440797 (2002-08-01), Wu et al.
patent: 6469343 (2002-10-01), Miura et al.
patent: 6512696 (2003-01-01), Fan et al.
patent: 6617639 (2003-09-01), Wang et al.
patent: 6653712 (2003-11-01), Knall et al.
patent: 6653733 (2003-11-01), Gonzalez et al.
patent: 6709928 (2004-03-01), Jenne et al.
patent: 6720630 (2004-04-01), Mandelman et al.
patent: 6737675 (2004-05-01), Patel et al.
patent: 6740928 (2004-05-01), Yoshii et al.
patent: 6768661 (2004-07-01), Vyvoda et al.
patent: 6784480 (2004-08-01), Bhattacharyya
patent: 6818558 (2004-11-01), Rathor et al.
patent: 6841813 (2005-01-01), Walker et al.
patent: 6849905 (2005-02-01), Ilkbahar et al.
patent: 6858899 (2005-02-01), Mahajani et al.
patent: 6897533 (2005-05-01), Yang et al.
patent: 6912163 (2005-06-01), Zheng et al.
patent: 6977201 (2005-12-01), Jung et al.
patent: 7005349 (2006-02-01), Lee et al.
patent: 7057234 (2006-06-01), Tiwari
patent: 7075828 (2006-07-01), Lue et al.
patent: 7115469 (2006-10-01), Halliyal et al.
patent: 7115942 (2006-10-01), Wang
patent: 7129538 (2006-10-01), Lee et al.
patent: 7133313 (2006-11-01), Shih et al.
patent: 7151692 (2006-12-01), Wu
patent: 7164603 (2007-01-01), Shih et al.
patent: 7187590 (2007-03-01), Zous et al.
patent: 7190614 (2007-03-01), Wu
patent: 7209390 (2007-04-01), Lue et al.
patent: 7250646 (2007-07-01), Walker et al.
patent: 7399674 (2008-07-01), Chen et al.
patent: 7442988 (2008-10-01), Oh et al.
patent: 7646056 (2010-01-01), Choi et al.
patent: 2001/0055838 (2001-12-01), Walker et al.
patent: 2003/0030100 (2003-02-01), Lee et al.
patent: 2003/0032242 (2003-02-01), Lee et al.
patent: 2003/0042534 (2003-03-01), Bhattacharyya
patent: 2003/0047755 (2003-03-01), Lee et al.
patent: 2003/0146465 (2003-08-01), Wu
patent: 2003/0224564 (2003-12-01), Kang et al.
patent: 2004/0079983 (2004-04-01), Chae et al.
patent: 2004/0108512 (2004-06-01), Iwata et al.
patent: 2004/0119122 (2004-06-01), Ilkbahar et al.
patent: 2004/0183126 (2004-09-01), Bae et al.
patent: 2004/0256679 (2004-12-01), Hu
patent: 2005/0006696 (2005-01-01), Noguchi et al.
patent: 2005/0023603 (2005-02-01), Eldridge et al.
patent: 2005/0062098 (2005-03-01), Mahajani et al.
patent: 2005/0074937 (2005-04-01), Jung
patent: 2005/0093054 (2005-05-01), Jung
patent: 2005/0145926 (2005-07-01), Lee et al.
patent: 2005/0219906 (2005-10-01), Wu
patent: 2005/0227435 (2005-10-01), Oh et al.
patent: 2005/0237801 (2005-10-01), Shih
patent: 2005/0237809 (2005-10-01), Shih et al.
patent: 2005/0237813 (2005-10-01), Zous et al.
patent: 2005/0237815 (2005-10-01), Lue et al.
patent: 2005/0237816 (2005-10-01), Lue et al.
patent: 2005/0270849 (2005-12-01), Lue
patent: 2005/0281085 (2005-12-01), Wu
patent: 2006/0198189 (2006-09-01), Lue et al.
patent: 2006/0198190 (2006-09-01), Lue
patent: 2006/0202252 (2006-09-01), Wang et al.
patent: 2006/0202261 (2006-09-01), Lue et al.
patent: 2006/0258090 (2006-11-01), Bhattacharyya et al.
patent: 2006/0261401 (2006-11-01), Bhattacharyya
patent: 2006/0281260 (2006-12-01), Lue
patent: 2007/0012988 (2007-01-01), Bhattacharyya
patent: 2007/0029625 (2007-02-01), Lue et al.
patent: 2007/0031999 (2007-02-01), Ho et al.
patent: 2007/0045718 (2007-03-01), Bhattacharyya
patent: 2007/0069283 (2007-03-01), Shih et al.
patent: 2007/0138539 (2007-06-01), Wu et al.
patent: 0016246 (1980-10-01), None
patent: 1411555 (2004-04-01), None
patent: 01677311 (2006-07-01), None
patent: 01677312 (2006-07-01), None
patent: 57100749 (1982-06-01), None
patent: 59074680 (1984-04-01), None
patent: 11040682 (1999-02-01), None
patent: 2002368141 (2002-12-01), None
patent: 2004363329 (2004-12-01), None
Sung et al., “Multi-Layer SONOS with Direct Tunnel Oxide for High Speed and Long Retention Time,” IEEE Silicon Nanoelectronics Workshop, Jun. 2002, pp. 83-84.
Aminzadeh et al., “Conduction and Charge Trapping in Polysilicon-Silicon Nitride-Oxide-Silicon Structures under Positive Gate Bias,” IEEE Trans. on Electron Dev. 35(4) Apr. 1998 459-467.
Baik, Seung, et al., “High Speed and Nonvolatile Si Nanocrystal Memory for Scaled Flash Technology using Highly Field-Sensitive Tunnel Barrier,” IEEE IEDM 03-545 22.3.1-22.3.4, 2003.
Blomme et al., “Multilayer tunneling barriers for nonvolatile memory applications,” Device Research Conf, 2002 60th DRC Digest 153-154.
Blomme et al., “Write/Erase Cycling Endurance of Memory Cells with SiO2/HfO2 Tunnel Dielectric,” IEEE Trans. on Dev. and Mterials Reliability 4(3), Sep. 2004 345-351.
Buckley, J., et al., “Engineering of ‘Conduction Band-Crested Barriers’ or ‘Dielectric Constant-Crested Barriers’ in view of their application of floating-gate non-volatile memory devices,” VLSI 2004, 55-56.
Chindalore, et al., “A New Combination-Erase Technique for Erasing Nitride Based (SONOS) Nonvolatile Memories,” IEEE Electron Dev. Lett 24(4) Apr. 2003, 257-259.
Cho, et al., “Simultaneous Hot-Hole Injection at Drain and Source for Efficient Erase and Excellent Endurance in SONOS Flash EEPROM Cells,” IEEE Electron Device Letters, vol. 24, No. 4, Apr. 2003, 260-262.
DiMaria, D.J., et al., “Conduction Studies in Silicon Nitride: Dark Currents and Photocurrents,” IBM J. Res. Dev. May 1977, 227-244.
Eitan, et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” IEEE Electron Device Lett 21(11) Nov. 2000, 543-545.
Govoreanu et al., “An Investigation of the Electron Tunneling Leakage Current Through Ultrathin Oxides/High-k Gate Stacks at Inversion Conditions,” IEEE SISPAD Intl. Conf. Sep. 3-5, 2003 287-290.
Govoreanu et al., “Simulation of Nanofloating Gate Memory with High-k Stacked Dielectrics,” IEEE SISPAD Intl. Conf. Sep. 3-5, 2003 299-302.
Govoreanu et al., “VARIOT: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices,” IEEE Electron Dev. Lett. 24(2) Feb. 2003 94-10.
Hijiya, S., et al., “High-Speed Write/Erase EAROM Cell with Graded Energy Band-Gap Insulator,” Electronics and Communications in Japan, Part 2, vol. 68, No. 2, Jun. 6, 1984, 28-36.
Hinkle, C.L., et al., “Enhanced tunneling in stacked gate dielectrics with ultra-thin HfO2 (ZrO2) layers sandwiched between thicker SiO2 layers,” Surface Science, Sep. 20, 2004, vol. 566-568, 1185-1189.
Ito, et al., “A Novel MNOS Technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications.” 2004 Symp. on VLSI Tech Dig. of Papers 2004, 80-81.
Kim et al., “Robust Multi-Bit Programmable Flash Memory Using a Resonant Tunnel Barrier,” Electron Dev. Mtg. Dec. 5-7, 2005, IEDM Technical Digest 861-864.
Lee, Chang, et al., “A Novel SONOS Structure of SiO2/SiN/Al203 with TaN Metal Gate for Multi-Giga Bit Flash Memories,” IEEE 2003 4 pages, 2003.
Lee, Chungho, et al., “Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Single-and Double-Layer Metal Nanoc

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Stacked non-volatile memory device and methods for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stacked non-volatile memory device and methods for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked non-volatile memory device and methods for... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2678842

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.