Network on chip with a low latency, high bandwidth...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

Reexamination Certificate

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C710S022000, C711S122000, C370S458000

Reexamination Certificate

active

07913010

ABSTRACT:
A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), and bus interface controllers (108); each IP block adapted to the data communications bus through a memory communications controller and a bus interface controller; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between an IP block and memory; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between one of the IP blocks and other IP blocks; each IP block adapted to the data communications bus by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.

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