High compressive stress carbon liners for MOS devices

Details High compressive stress carbon liners for MOS devices High compressive stress carbon liners for MOS devices

2011-03-15

2011-03-15

Toledo, Fernando L (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S288000, C257S327000, C438S197000

Reexamination Certificate

active

07906817

ABSTRACT:
Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.

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