Memory apparatus

Details Memory apparatus Memory apparatus

2011-08-09

2011-08-09

Dickey, Thomas L (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29300, C257SE21280

Reexamination Certificate

active

07994562

ABSTRACT:
The memory apparatus includes a memory device including a gate insulating layer formed on a silicon substrate by sequentially stacking a tunnel oxide layer, a charge trap layer, and a block oxide layer in this order, on the silicon substrate. In addition, a gate electrode is formed on the gate insulating layer. The block oxide layer is formed by stacking a first block oxide layer and a second block oxide layer, wherein the first block oxide layer is adjacent to the charge trap layer and the second block oxide layer is adjacent to the gate electrode. The second block oxide layer is formed of a dielectric material having higher permittivity than that of the first block oxide layer and having higher electron affinity than that of the first block oxide layer.

REFERENCES:
patent: 2005/0093054 (2005-05-01), Jung
patent: 2001-358237 (2001-12-01), None
patent: 2002-280467 (2002-09-01), None
patent: 2003-068897 (2003-03-01), None
patent: 2004-336044 (2004-11-01), None
patent: 2005-005715 (2005-01-01), None
patent: 2009-081316 (2009-04-01), None
patent: 10-2006-0104717 (2006-10-01), None
patent: 10-2008-0060609 (2008-07-01), None
Japanese Office Action—2008-184786 dated Jun. 1, 2010.
Notice of Preliminary Rejection issued by the Korean Intellectual Property Office on Mar. 14, 2011, citing KR10-2008-0060609 and KR10-2006-0104717.

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