Method of forming a semiconductor device featuring a gate...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation

Reexamination Certificate

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C438S585000, C438S588000, C438S591000

Reexamination Certificate

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07960243

ABSTRACT:
A semiconductor device (10) is formed in a semiconductor layer (12). A gate stack (16,18) is formed over the semiconductor layer and comprises a first conductive layer (22) and a second layer (24) over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species (46) is implanted into the second layer. Source/drain regions (52) are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.

REFERENCES:
patent: 4356041 (1982-10-01), Kosa
patent: 4495219 (1985-01-01), Kato et al.
patent: 4755865 (1988-07-01), Wilson et al.
patent: 6278165 (2001-08-01), Oowaki et al.
patent: 6380014 (2002-04-01), Ohta et al.
patent: 6461984 (2002-10-01), Han et al.
patent: 6468915 (2002-10-01), Liu
patent: 6808974 (2004-10-01), Park et al.
patent: 7151023 (2006-12-01), Nayfeh et al.
patent: 7279413 (2007-10-01), Park et al.
patent: 7368356 (2008-05-01), Li
patent: 7498643 (2009-03-01), Kamimuta et al.
patent: 2003/0111699 (2003-06-01), Wasshuber et al.
patent: 2004/0023478 (2004-02-01), Samavedam et al.
patent: 2004/0178470 (2004-09-01), Hieda
patent: 2005/0037596 (2005-02-01), Erokhin et al.
patent: 2005/0056887 (2005-03-01), Tran
patent: 2005/0112857 (2005-05-01), Gluschenkov et al.
patent: 2005/0266631 (2005-12-01), Kim et al.
patent: 2005/0282325 (2005-12-01), Belyansky et al.
patent: 2006/0011990 (2006-01-01), Furukawa et al.
patent: 2006/0017112 (2006-01-01), Wang et al.
patent: 2006/0043497 (2006-03-01), Kimizuka et al.
patent: 2006/0068556 (2006-03-01), Noda
patent: 2006/0138541 (2006-06-01), Nakamura et al.
patent: 2006/0145274 (2006-07-01), Chidambarrao et al.
patent: 2006/0160317 (2006-07-01), Zhu et al.
patent: 2006/0163678 (2006-07-01), Anezaki
patent: 2006/0172497 (2006-08-01), Hareland et al.
patent: 2006/0282325 (2006-12-01), Martin
patent: 2006/0286747 (2006-12-01), Mouli et al.
patent: 2007/0042547 (2007-02-01), Kikuchi et al.
patent: 2007/0161170 (2007-07-01), Orlowski et al.
patent: 2007/0166970 (2007-07-01), Triyoso et al.
patent: 1998144880 (1998-05-01), None
International Search Report and Written Opinion for correlating PCT Patent Application No. PCT/US2008/064105 dated Sep. 26, 2008.

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