System and method for a DDR SDRAM controller

Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting

Reexamination Certificate

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C710S100000, C710S315000, C710S307000

Reexamination Certificate

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07921243

ABSTRACT:
A buffer control system for a data storage device controller comprises a command module and a burst module. The command module receives first channel data from a first channel having a first data format and second channel data from a second channel having a second data format and converts the first channel data and the second channel data to respective data packets each having a third data format that is different than the first data format and the second data format. The burst module that selectively transmits the data packets having the third data format to a memory in a single write burst.

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